Engineers/ Sr. Engineers- Mechanical Engineers
Posted today
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Job Description
Epergne Solutions is looking for Engineers/ Sr. Engineers
Location: Mysore, Mumbai
Must have Skills: Designing Switch boards
Job Description:
Bachelors Deg. In Mechanical Engineering
3 to 7 years of experience in design/development of ANSI LV and MV Products
Hands on experience in 3D Modelling on the job
Ability to design models of parts and assemblies from concept to completed 3D (NX Preferred) model and AutoCAD software.
Experience working with sheet metal parts, bus bars, insulation parts, etc.
Experience in working with complex made to order manufacturing environment.
Ability to analyze customer s technical specifications for LV/MV Switchgear /MCC Products and work closely with Engineering Project team to ensure delivery of complete and optimal product.
Ability to take overall mechanical ownership of the project and create Mech. BOM, develop new assemblies, validate functionality and release parts/assemblies to production.
Able to work and manage a small team.
Familiar with ANSI/IEEE standards for MV/LV Switchgears/MCCs (IEEE C37.20.2, IEEE C37.20.3, IEEE- C37.20.7, UL 845).
Knowledge on Electrical CAD tools: ACAD, NX (3D CAD), Teamcenter would be an advantage.
Engineers /Sr. Engineers
Posted today
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Job Description
Epergne Solutions is looking for Engineers /Sr. Engineer
Location : Mysore/ Bengaluru
Position: Fulltime
Roles and Qualifications:
- Expert level experience of Working in Creo
- Modules like 3D Modeling, Detailing, Assembly, Sheetmetal.
- Creation of Family Tables & Managing large Assemblies & Configurations.
- MBD Experience.
- Hands on Experience in Solidworks.
- Experience in design of plastics/Sheet metal parts
- Knowledge on manufacturing processes
- Strong in GD&T and manufacturing drawing creation.
- Manufacturing process - Metal punching, bending, roll forming and deep drawing, injection moulding.
- Good experience in CAD packages Pro/E or Solid works (Solid modelling, Surface modelling, Detailing).
- Exposure to PDM/PLM (Windchill) system.
Experience: 4 - 9 Years
Other Skills:
Good Oral and written communication.
- Team player and self-driven/Motivated
- Team Management Skills.
Job Description:
- Understanding technical requirements and Executing CAD projects in Creo & Solid works as per the timelines and quality standards specified by customer
- Project Estimation & Planning.
- Review of Deliverables from team.
- Drive all aspects of the project, ensuring team members remain on track and deviations are effectively addressed.
Preferred candidates who can join us within 30 days
Engineers /Sr. Engineers
Posted today
Job Viewed
Job Description
Epergne Solutions is looking for Engineers /Sr. Engineer
Location : Mysore/ Bengaluru
Position: Fulltime
Roles and Qualifications:
- Expert level experience of Working in Creo
- Modules like 3D Modeling, Detailing, Assembly, Sheetmetal.
- Creation of Family Tables & Managing large Assemblies & Configurations.
- MBD Experience.
- Hands on Experience in Solidworks.
- Experience in design of plastics/Sheet metal parts
- Knowledge on manufacturing processes
- Strong in GD&T and manufacturing drawing creation.
- Manufacturing process - Metal punching, bending, roll forming and deep drawing, injection moulding.
- Good experience in CAD packages Pro/E or Solid works (Solid modelling, Surface modelling, Detailing).
- Exposure to PDM/PLM (Windchill) system.
Experience: 4 - 9 Years
Other Skills:
Good Oral and written communication.
- Team player and self-driven/Motivated
- Team Management Skills.
Job Description:
- Understanding technical requirements and Executing CAD projects in Creo & Solid works as per the timelines and quality standards specified by customer
- Project Estimation & Planning.
- Review of Deliverables from team.
- Drive all aspects of the project, ensuring team members remain on track and deviations are effectively addressed.
Preferred candidates who can join us within 30 days
DFT Engineers
Posted 9 days ago
Job Viewed
Job Description
ATPG DFT Lead Engineers
Experience: 7 to 10 years
Location: Bangalore
Job Description:
· Implementation and verification of DFT architecture and features
· Scan insertion and ATPG pattern generation
· ATPG patterns verification with gate-level simulation
· Test coverage and test cost reduction analysis
· Post silicon support to ensure successful bring up and enhance yield learning
Preferred Experience:
· Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
· Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
· Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Academic Credentials:
· Bachelors or Masters degree in computer engineering/Electrical Engineering.
Interested please share your updated resume to
STA Engineers
Posted 9 days ago
Job Viewed
Job Description
Required Skills:
- Proficiency in Static Timing Analysis (STA)
- Experience with block-level and top-level timing closure (BCLP)
- Knowledge of Logical Equivalence Check (LEC)
- Ability to write and debug SDC constraints
Location: Bangalore, Hyderabad, Chennai, Noida
Experience: 4+ years
FPGA Engineers
Posted 9 days ago
Job Viewed
Job Description
JD
- 3+ Years of experience
- Good FPGA RTL coding skills with strong basics design concepts
- Hands on experience in FPGA tools like Vivado
- Understanding of SoCs will be an advantage
- Experience is any of the Emulation/Prototyping platforms -Like Veloce, HAPS, Protium
- Good Communication skills
Notice period - 0-30 Days
STA Engineers
Posted today
Job Viewed
Job Description
Required Skills:
- Proficiency in Static Timing Analysis (STA)
- Experience with block-level and top-level timing closure (BCLP)
- Knowledge of Logical Equivalence Check (LEC)
- Ability to write and debug SDC constraints
Location: Bangalore, Hyderabad, Chennai, Noida
Experience: 4+ years
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DFT Engineers
Posted 1 day ago
Job Viewed
Job Description
Experience: 7 to 10 years
Location: Bangalore
Job Description:
· Implementation and verification of DFT architecture and features
· Scan insertion and ATPG pattern generation
· ATPG patterns verification with gate-level simulation
· Test coverage and test cost reduction analysis
· Post silicon support to ensure successful bring up and enhance yield learning
Preferred Experience:
· Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
· Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
· Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
Academic Credentials:
· Bachelors or Masters degree in computer engineering/Electrical Engineering.
Interested please share your updated resume to
STA Engineers
Posted 2 days ago
Job Viewed
Job Description
- Proficiency in Static Timing Analysis (STA)
- Experience with block-level and top-level timing closure (BCLP)
- Knowledge of Logical Equivalence Check (LEC)
- Ability to write and debug SDC constraints
Location: Bangalore, Hyderabad, Chennai, Noida
Experience: 4+ years
FPGA Engineers
Posted 10 days ago
Job Viewed
Job Description
3+ Years of experience
Good FPGA RTL coding skills with strong basics design concepts
Hands on experience in FPGA tools like Vivado
Understanding of SoCs will be an advantage
Experience is any of the Emulation/Prototyping platforms -Like Veloce, HAPS, Protium
Good Communication skills
Notice period - 0-30 Days