9 Leadership Skills jobs in India

Leverage PageGroup's Platform to Scale Your Technology Portfolio & Lead a P&L

Exceptional Career Growth for Entrepreneurial Technology Talent

About Our Client

PageGroup is one of the world's largest and most successful professional recruitment and talent advisory firms, with 165 offices across 37 countries. Michael Page, our flagship brand, is a market leader in mid-to-senior level hiring across APAC and globally. We are a FTSE 250 organisation, backed by over 45 years of credibility and delivery.

In India, Page has grown rapidly to become the partner of choice for CXOs and senior leaders across technology, industrial, consumer, and financial services.

Within technology, we work with organisations across SaaS, enterprise software, product development, AI/ML, cloud, cybersecurity, and other innovation-led domains.

Our approach is consultative, data-informed, and rooted in long-term relationships. We are recognised among India's Best Workplaces for Women and hold Great Place to Work® Certification.

Job Description

We are looking to engage with experienced leaders at the Associate Director / Director level - professionals with a strong pedigree in recruitment, search, or adjacent advisory environments. This is a chance to:

Build and lead your own technology-focused portfolio within an established, high-performing practice area

Partner with organisations in SaaS, enterprise technology, product development, AI/ML, cloud, cybersecurity, and other innovation-led domains

Drive business development at senior levels - influencing hiring strategies at the CIO, CTO, CDO, CHRO, and CEO level

Partner with organisations in high-growth tech sectors including SaaS, enterprise platforms, digital transformation, and emerging technologies

Deliver on senior retained and exclusive mandates, leveraging Page's brand equity, proprietary tools, and delivery infrastructure

Collaborate directly with senior leadership and regional heads to shape strategy, scale your vertical, and capture market share

Take ownership of your growth path - leadership here is defined by external influence, client relationships, and commercial impact, not just hierarchy

The Successful Applicant

This opportunity is ideal for professionals who are:

Currently managing senior delivery in retained or contingent search models

Adept at building trusted relationships with C-level stakeholders

Ready to evolve into a strategic, commercially empowered role

Looking to transition into full P&L ownership over time

Drawn to the idea of building something substantial within a global brand

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ We are seeking a highly experienced and innovative Fellow to join our CPU Cores team. You will drive power innovations, strategies, methodologies, and estimation processes, setting industry standards. Your deep understanding of CPU architecture and power management techniques will be crucial in leading cross-functional teams to achieve cutting-edge power efficiency in our products. In this role, you will collaborate with RTL, verification, and engineering teams to integrate power-efficient solutions into our CPU cores. Your leadership and strategic vision will guide the development of methodologies that optimize power usage. Additionally, you will mentor team members and effectively communicate complex technical concepts to align stakeholders and drive successful implementation. Key Responsibilities Drive Power Innovations: Lead the development and implementation of innovative power management techniques and technologies to enhance the power efficiency of our CPU cores. Strategic Planning: Develop and execute power strategies that align with industry trends and company goals. Provide strategic direction for power-related projects and initiatives. Methodology Development: Create and refine methodologies for power estimation, analysis, and optimization. Ensure these methodologies are integrated into the design and development processes. End-to-End Power Management: Oversee the entire power management process from initial design to post-silicon validation. Ensure power efficiency is maintained throughout the product lifecycle. Cross-Functional Collaboration: Work closely with compiler teams, software teams, and other engineering groups to integrate power management techniques across all levels of the system. Cross-Functional Leadership: Collaborate with various teams, including design, verification, software, and product management, to ensure power efficiency goals are met. Provide technical guidance and mentorship to team members. Power Estimation and Analysis: Lead efforts in power estimation and analysis at different stages of the design cycle. Develop tools and models to predict and measure power consumption accurately. Post-Silicon Power Optimization: Lead efforts in post-silicon power analysis and optimization. Develop and implement strategies to address power issues identified during silicon validation. Innovation and Research: Foster a culture of innovation by encouraging research and experimentation in power management techniques. Identify opportunities for patents and publications. Industry Engagement: Stay abreast of the latest advancements in power management within the CPU industry. Represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Metrics: Define and track key performance indicators (KPIs) related to power efficiency. Report on progress and impact to senior leadership Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in CPU architecture, power management, or related areas. Proven track record of driving power innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of CPU core design, power management techniques, and power estimation methodologies. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to power management and CPU design. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in power management for CPUs #LI-SK5 CTERR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.We are seeking a highly experienced and innovative Fellow to join our CPU Cores team. You will drive power innovations, strategies, methodologies, and estimation processes, setting industry standards. Your deep understanding of CPU architecture and power management techniques will be crucial in leading cross-functional teams to achieve cutting-edge power efficiency in our products. In this role, you will collaborate with RTL, verification, and engineering teams to integrate power-efficient solutions into our CPU cores. Your leadership and strategic vision will guide the development of methodologies that optimize power usage. Additionally, you will mentor team members and effectively communicate complex technical concepts to align stakeholders and drive successful implementation. Key Responsibilities Drive Power Innovations: Lead the development and implementation of innovative power management techniques and technologies to enhance the power efficiency of our CPU cores. Strategic Planning: Develop and execute power strategies that align with industry trends and company goals. Provide strategic direction for power-related projects and initiatives. Methodology Development: Create and refine methodologies for power estimation, analysis, and optimization. Ensure these methodologies are integrated into the design and development processes. End-to-End Power Management: Oversee the entire power management process from initial design to post-silicon validation. Ensure power efficiency is maintained throughout the product lifecycle. Cross-Functional Collaboration: Work closely with compiler teams, software teams, and other engineering groups to integrate power management techniques across all levels of the system. Cross-Functional Leadership: Collaborate with various teams, including design, verification, software, and product management, to ensure power efficiency goals are met. Provide technical guidance and mentorship to team members. Power Estimation and Analysis: Lead efforts in power estimation and analysis at different stages of the design cycle. Develop tools and models to predict and measure power consumption accurately. Post-Silicon Power Optimization: Lead efforts in post-silicon power analysis and optimization. Develop and implement strategies to address power issues identified during silicon validation. Innovation and Research: Foster a culture of innovation by encouraging research and experimentation in power management techniques. Identify opportunities for patents and publications. Industry Engagement: Stay abreast of the latest advancements in power management within the CPU industry. Represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Metrics: Define and track key performance indicators (KPIs) related to power efficiency. Report on progress and impact to senior leadership Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in CPU architecture, power management, or related areas. Proven track record of driving power innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of CPU core design, power management techniques, and power estimation methodologies. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to power management and CPU design. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in power management for CPUs #LI-SK5 CTERR1
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Job Description: We are seeking a highly experienced and innovative Fellow to join our Physical Design (PD) Methodology team. The successful candidate will be responsible for driving advancements in PD methodologies, strategies, and tools to optimize the design and implementation of our semiconductor products. This role requires a deep understanding of physical design, EDA tools, and the ability to partner with cross-functional teams to achieve state-of-the-art design efficiency and performance. Key Responsibilities: Drive PD Methodology Innovations: Lead the development and implementation of cutting-edge physical design methodologies to enhance design efficiency, performance, and manufacturability. Strategic Planning: Develop and execute strategies that align with industry trends and company goals. Provide strategic direction for PD-related projects and initiatives. Methodology Development: Create and refine methodologies for physical design, including floorplanning, placement, routing, and timing closure. Ensure these methodologies are integrated into the design and development processes. End-to-End Design Optimization: Oversee the entire physical design process from initial concept to tape-out. Ensure design efficiency and performance are maintained throughout the product lifecycle. Cross-Functional Collaboration: Work closely with RTL design teams, verification teams, and other engineering groups to integrate physical design methodologies across all levels of the system. Vendor Engagement: Collaborate with EDA tool vendors such as Synopsys and Cadence to ensure tools meet our design requirements. Drive joint development efforts and influence tool enhancements. Tool and Flow Automation: Lead efforts in the development and optimization of EDA tools for physical design. Work with tool vendors to ensure the tools meet our design requirements. Signoff Enablement: Ensure that all physical design methodologies and processes meet signoff criteria for manufacturability and performance. Technology and Library Enablement: Work with technology and library teams to enable new technologies and libraries in the physical design flow. PPA Optimization Guidance: Provide guidance on optimizing power, performance, and area (PPA) during the physical design process. Debug and Support: Lead efforts in debugging design issues and providing support to design teams to resolve complex physical design challenges. Industry Engagement: Stay abreast of the latest advancements in physical design within the semiconductor industry. Represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Cross-Functional Leadership: Collaborate with various teams, including design, verification, software, and product management, to ensure physical design goals are met. Provide technical guidance and mentorship to team members. Innovation and Research: Foster a culture of innovation by encouraging research and experimentation in physical design techniques. Identify opportunities for patents and publications. Metrics: Define and track key performance indicators (KPIs) related to physical design efficiency and performance. Report on progress and impact to senior leadership. Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in physical design, EDA tools, or related areas. Proven track record of driving PD methodology innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of physical design, EDA tools, and design optimization techniques. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to physical design and EDA tools. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in physical design for semiconductors #LI-SK5 CTERR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Job Description: We are seeking a highly experienced and innovative Fellow to join our Physical Design (PD) Methodology team. The successful candidate will be responsible for driving advancements in PD methodologies, strategies, and tools to optimize the design and implementation of our semiconductor products. This role requires a deep understanding of physical design, EDA tools, and the ability to partner with cross-functional teams to achieve state-of-the-art design efficiency and performance. Key Responsibilities: Drive PD Methodology Innovations: Lead the development and implementation of cutting-edge physical design methodologies to enhance design efficiency, performance, and manufacturability. Strategic Planning: Develop and execute strategies that align with industry trends and company goals. Provide strategic direction for PD-related projects and initiatives. Methodology Development: Create and refine methodologies for physical design, including floorplanning, placement, routing, and timing closure. Ensure these methodologies are integrated into the design and development processes. End-to-End Design Optimization: Oversee the entire physical design process from initial concept to tape-out. Ensure design efficiency and performance are maintained throughout the product lifecycle. Cross-Functional Collaboration: Work closely with RTL design teams, verification teams, and other engineering groups to integrate physical design methodologies across all levels of the system. Vendor Engagement: Collaborate with EDA tool vendors such as Synopsys and Cadence to ensure tools meet our design requirements. Drive joint development efforts and influence tool enhancements. Tool and Flow Automation: Lead efforts in the development and optimization of EDA tools for physical design. Work with tool vendors to ensure the tools meet our design requirements. Signoff Enablement: Ensure that all physical design methodologies and processes meet signoff criteria for manufacturability and performance. Technology and Library Enablement: Work with technology and library teams to enable new technologies and libraries in the physical design flow. PPA Optimization Guidance: Provide guidance on optimizing power, performance, and area (PPA) during the physical design process. Debug and Support: Lead efforts in debugging design issues and providing support to design teams to resolve complex physical design challenges. Industry Engagement: Stay abreast of the latest advancements in physical design within the semiconductor industry. Represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Cross-Functional Leadership: Collaborate with various teams, including design, verification, software, and product management, to ensure physical design goals are met. Provide technical guidance and mentorship to team members. Innovation and Research: Foster a culture of innovation by encouraging research and experimentation in physical design techniques. Identify opportunities for patents and publications. Metrics: Define and track key performance indicators (KPIs) related to physical design efficiency and performance. Report on progress and impact to senior leadership. Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in physical design, EDA tools, or related areas. Proven track record of driving PD methodology innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of physical design, EDA tools, and design optimization techniques. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to physical design and EDA tools. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in physical design for semiconductors #LI-SK5 CTERR1
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.