282 Senior Dft Lead jobs in India

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSI

Experience: 5 - 25 years

Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune

Education: Engineering (excluding Mechanical/Civil)

Detailed JD:

5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one Full chip DFT •Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSI

Experience: 5 - 25 years

Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune

Education: Engineering (excluding Mechanical/Civil)

Detailed JD:

5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one Full chip DFT •Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSI

Experience: 5 - 25 years

Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune

Education: Engineering (excluding Mechanical/Civil)

Detailed JD:

5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one Full chip DFT •Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim

DFT Lead :

Work Location - Bangalore

Experience - 7+ Years

Desired Skills and Experience –

· 7+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.

· DFT logic integration and verification.

· Experience in debugging low coverage and DRC fixes

· Gate Level ATPG simulation with and without timing.

· Pattern generation, verification, and delivery to ATE team.

· Post silicon debug and support on failing patterns.

· Good experience with tools from Synopsys like TestMAX

· Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process

· Excellent problem-solving and debugging skills. Proactive in nature.

Leading junior teams, Mentoring/Training, and Project leadership.

Job Overview

Arm’s DFT methodology team works on DFT flows and methodology for projects, including soft IP, hard macros, SOCs and physical library IP across all the Arm design sites. In addition, this team builds and drives DFT methodology and flows throughout all of Arm and works to get support from EDA vendors to support our methodologies.

Responsibilities:

Support DFT on multiple types of projects in multiple design centers and apply innovative DFT techniques and affect the content of forthcoming CPU, GPU, ML and systems IP, SOCs some years before they appear in mainstream products. This candidate will contribute to DFT methodology by crafting flows, evaluating tool capabilities, helping other specialists on projects, detailing work through documentation, working with EDA vendors and propagating DFT methodologies. This position may also include meeting with customers for DFT training or to address DFT concerns. The candidate will be the first recruit in the DFT methodology group in Bangalore and will be responsible for leading the team in bangalore.

Required Skills And Experience:

• This role is for a Principal DFT engineer with 12 years plus experience
• Technical leadership in DFT and ability to train/work with junior team members
• Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows
• Proficient in Unix/Linux environments
• One or more core DFT skills are considered crucial for this position including some of the following
• Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations.
• Experience with Siemens, Cadence and/or Synopsys DFT tools
• Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area.

“Nice To Have” Skills and Experience :

• Familiarity with IEEE standards such as 1500, 1149.1, 1687 and 1838
• Familiarity with supporting silicon into volume production
• Knowledge of SSN and 3DIC
• Gained some exposure to digital ASIC frontend and backend design & verification processes
• Hands-on Synthesis and Static Timing Analysis (STA) experience
• Familiarity with SOC architectures (Auto/Infrastructure/Client) and low power design practices would be an advantage
• Understanding of Functional Safety as it applies to DFT
• Working knowledge of Siemens MBIST and LBIST tools
• Exposure to simulation and formal verification tools
• Exposure to AI tools for execution
• Exposure Arm MBIST interface

In Return

You will be provided with the training and environment to succeed in this role. As well as a friendly and high-performance working environment, Arm offers a competitive benefits package including private medical insurance, sabbatical, supplementary pension, and wellness benefits. We are offering a hybrid approach to home and office working to provide an adaptable experience for all employees and to promote a strong collaborative environment.

Design for Testability (DFT) Engineer (Senior Level - 10+ years’ experience)

Company: HCL Tech

Job Summary:

We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the implementation of robust test strategies. You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits.

Responsibilities:

• Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimization
• Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniques
• Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection rates
• Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimization
• Lead and mentor junior DFT engineers, fostering a culture of excellence and knowledge sharing within the team
• Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test quality
• Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologies
• Manage and maintain DFT libraries and internal DFT standards
• Contribute to the continuous improvement of the DFT flow within the team

Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
• Minimum of 10+ years of experience in Design for Testability (DFT) for complex ASICs and SoCs
• Proven track record of successfully leading and implementing DFT strategies for high-volume production
• In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability, Design for Power, etc.)
• Expertise in industry-standard DFT tools (Synopsys DFT Compiler, TetraMAX, etc.) and scripting languages (Perl, TCL) for automation
• Strong understanding of digital design principles (combinational logic, sequential logic) and manufacturing test processes
• Excellent analytical and problem-solving skills with a focus on achieving optimal test quality and cost-effectiveness
• Effective leadership, communication, collaboration, and teamwork skills

Benefits:

• Competitive salary and benefits package commensurate with experience and expertise
• Opportunity to lead and influence the DFT strategy for cutting-edge technologies
• Dynamic and challenging work environment with opportunities for professional growth and leadership development
• Recognition and rewards for outstanding contributions