12,978 Ams Verification Engineer Lead jobs in India

Technical Skills2-5 years of experience in mixed-signal design verification and at least 2 years of experience managing a team of verification engineers.Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.Writing and maintaining Analog Mixed Signal models, using real number modelling and Verilog AMS.Experienced in setting up and maintaining mixed signal testbench from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or modelsExperience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium , VIVA & SimvisionExpertise in Cadence Spectre simulation test bench development, Regression Flow & debugExpertise in mixed-signal waveform review, debugging, and coverage analysis.Strong understanding of Unix environment and shell scripting, alongside working knowledge of Python & automation skillsExperience with functionally safe design verification and fault injection is highly desirable.Non-Technical SkillsExcellent verbal and written communication skills in English.In-depth understanding of organizational objectives, with keen insights into business trends and market conditions.Awareness and sensitivity to cross-cultural dynamics.Results-oriented and able to meet aggressive timelinesMentor & develop technical talentsProvide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.Effectively manage project tasks and issues using JIRA, showcasing strong organizational and tracking abilities.

Technical Skills

• 2-5 years of experience in mixed-signal design verification and at least 2 years of experience managing a team of verification engineers.
• Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.
• Writing and maintaining Analog Mixed Signal models, using real number modelling and VerilogAMS.
• Experienced in setting up and maintaining mixed signal testbench from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.
• Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or models
• Experience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium , VIVA & Simvision
• Expertise in Cadence Spectre simulation test bench development, Regression Flow & debug
• Expertise in mixed-signal waveform review, debugging, and coverage analysis.
• Strong understanding of Unix environment and shell scripting, alongside working knowledge of Python & automation skills
• Experience with functionally safe design verification and fault injection is highly desirable.

Non-Technical Skills

• Excellent verbal and written communication skills in English.
• In-depth understanding of organizational objectives, with keen insights into business trends and market conditions.
• Awareness and sensitivity to cross-cultural dynamics.
• Results-oriented and able to meet aggressive timelines
• Mentor & develop technical talents
• Provide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.
• Effectively manage project tasks and issues using JIRA, showcasing strong organizational and tracking abilities.

Technical Skills

• 2-5 years of experience in mixed-signal design verification and at least 2 years of experience managing a team of verification engineers.
• Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.
• Writing and maintaining Analog Mixed Signal models, using real number modelling and VerilogAMS.
• Experienced in setting up and maintaining mixed signal testbench from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.
• Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or models
• Experience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium , VIVA & Simvision
• Expertise in Cadence Spectre simulation test bench development, Regression Flow & debug
• Expertise in mixed-signal waveform review, debugging, and coverage analysis.
• Strong understanding of Unix environment and shell scripting, alongside working knowledge of Python & automation skills
• Experience with functionally safe design verification and fault injection is highly desirable.

Non-Technical Skills

• Excellent verbal and written communication skills in English.
• In-depth understanding of organizational objectives, with keen insights into business trends and market conditions.
• Awareness and sensitivity to cross-cultural dynamics.
• Results-oriented and able to meet aggressive timelines
• Mentor & develop technical talents
• Provide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.
• Effectively manage project tasks and issues using JIRA, showcasing strong organizational and tracking abilities.

Skills/Experience :

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.

Responsibilities :

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.

Education Requirements :

• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field

Skills/Experience :

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.

Responsibilities :

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.

Education Requirements :

• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field