463 Analog Mixed Signal jobs in India

Technical Skills2-5 years of experience in mixed-signal design verification and at least 2 years of experience managing a team of verification engineers.Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.Writing and maintaining Analog Mixed Signal models, using real number modelling and Verilog AMS.Experienced in setting up and maintaining mixed signal testbench from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or modelsExperience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium , VIVA & SimvisionExpertise in Cadence Spectre simulation test bench development, Regression Flow & debugExpertise in mixed-signal waveform review, debugging, and coverage analysis.Strong understanding of Unix environment and shell scripting, alongside working knowledge of Python & automation skillsExperience with functionally safe design verification and fault injection is highly desirable.Non-Technical SkillsExcellent verbal and written communication skills in English.In-depth understanding of organizational objectives, with keen insights into business trends and market conditions.Awareness and sensitivity to cross-cultural dynamics.Results-oriented and able to meet aggressive timelinesMentor & develop technical talentsProvide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.Effectively manage project tasks and issues using JIRA, showcasing strong organizational and tracking abilities.

Technical Skills

• 2-5 years of experience in mixed-signal design verification and at least 2 years of experience managing a team of verification engineers.
• Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.
• Writing and maintaining Analog Mixed Signal models, using real number modelling and VerilogAMS.
• Experienced in setting up and maintaining mixed signal testbench from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.
• Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or models
• Experience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium , VIVA & Simvision
• Expertise in Cadence Spectre simulation test bench development, Regression Flow & debug
• Expertise in mixed-signal waveform review, debugging, and coverage analysis.
• Strong understanding of Unix environment and shell scripting, alongside working knowledge of Python & automation skills
• Experience with functionally safe design verification and fault injection is highly desirable.

Non-Technical Skills

• Excellent verbal and written communication skills in English.
• In-depth understanding of organizational objectives, with keen insights into business trends and market conditions.
• Awareness and sensitivity to cross-cultural dynamics.
• Results-oriented and able to meet aggressive timelines
• Mentor & develop technical talents
• Provide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.
• Effectively manage project tasks and issues using JIRA, showcasing strong organizational and tracking abilities.

Technical Skills

• 2-5 years of experience in mixed-signal design verification and at least 2 years of experience managing a team of verification engineers.
• Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.
• Writing and maintaining Analog Mixed Signal models, using real number modelling and VerilogAMS.
• Experienced in setting up and maintaining mixed signal testbench from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.
• Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or models
• Experience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium , VIVA & Simvision
• Expertise in Cadence Spectre simulation test bench development, Regression Flow & debug
• Expertise in mixed-signal waveform review, debugging, and coverage analysis.
• Strong understanding of Unix environment and shell scripting, alongside working knowledge of Python & automation skills
• Experience with functionally safe design verification and fault injection is highly desirable.

Non-Technical Skills

• Excellent verbal and written communication skills in English.
• In-depth understanding of organizational objectives, with keen insights into business trends and market conditions.
• Awareness and sensitivity to cross-cultural dynamics.
• Results-oriented and able to meet aggressive timelines
• Mentor & develop technical talents
• Provide frequent reports on progress status and roadblocks, ensuring transparent communication with stakeholders.
• Effectively manage project tasks and issues using JIRA, showcasing strong organizational and tracking abilities.

Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD

Location: Bangalore

Job Title: Senior Analog Mixed-Signal Design Engineer

Location: Bangalore, India

Desired Education Level: Graduate / Doctorate and above

Years of experience: MTech/MS with 5 years of experience or Ph.D. with 2 years

About us

We are the precision timing company. Our semiconductor MEMS

programmable solutions offer a rich feature set that enables customers to differentiate

their products with higher performance, smaller size, lower power and better reliability.

With more than 3 billion devices shipped, We are changing the timing industry

Job Summary

Responsibilities:

• Develop analog and mixed-signal architectures and circuits in CMOS processes

• Analyze technology, architecture, circuit design, and parametric design trade-offs to

meet aggressive technical performance specifications

Perform transistor-level design and simulation using industry leading EDA tools

Lead comprehensive design reviews

• Supervise Analog Circuit Physical Design Layout and edit layouts

• Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test

Engineering and Applications teams to ensure DFT, DFM features and achieve rapid

silicon bring-up and time to production release

• Perform post-layout parasitic-extraction and back-annotated simulations to validate

design

• Perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality

and yields

• Participate in the bring-up of silicon prototypes

• Initiate Design-of Experiments for Root Cause Analysis, anomalous observations in

silicon across PVT conditions, and propose solutions

Qualifications & Requirements (Education must be included):

• MTech/M.S with minimum 5 years of relevant experience or Ph.D. with 2 years of

Relevant experience in Electrical Engineering

• Provel track record of taking at least one analog-mixed signal part to high-volume

production.•

Proven track record at each stage of the following:

• Circuit architecture development and technical feasibility studies

• Writing detailed block-level specifications and review documents

• Detailed design and simulation of one or more of the following:

Oscillators,

ADCs,

DACs,

temperature sensors,

Integer and Fractional-N PLLs,

Digital PLLs,

low-noise op-amps,

regulators,

bandgap circuits in CMOS.

• Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode

AMS tools, Layout XL

• Extensive knowledge of layout effects for circuit and layout design. Ability to

supervise layout designers

• Extensive experience with post-layout extraction and verifications

• Experience with validation, characterization, qualification, and adherence to

production release criteria

• Ability to communicate and work effectively with geographically dispersed teams of

mixed-signal, digital, verifications engineers

• Ability to work independently and drive solutions to challenging problems

Desired Characteristics & Attributes:

• An “ownership” mind set focusing on the overall success of the business.

• Can do” positive, enthusiastic attitude.

• Demonstrated analytical and problem-solving skills.

• Strong communication skills.

• Ability to work in teams and collaborate effectively with people in different functions.

• Ability to efficiently context – switch between multiple concurrent tasks.

We are a Equal Opportunity Employer.

Contact:

Uday

Mulya Technologies

"Mining The Knowledge Community"

Top100 Global Semiconductor Organization HQ in California. Revenue over 200 Million USD

Location: Bangalore

Job Title: Senior Analog Mixed-Signal Design Engineer

Location: Bangalore, India

Desired Education Level: Graduate / Doctorate and above

Years of experience: MTech/MS with 5 years of experience or Ph.D. with 2 years

About us

We are the precision timing company. Our semiconductor MEMS

programmable solutions offer a rich feature set that enables customers to differentiate

their products with higher performance, smaller size, lower power and better reliability.

With more than 3 billion devices shipped, We are changing the timing industry

Job Summary

Responsibilities:

• Develop analog and mixed-signal architectures and circuits in CMOS processes

• Analyze technology, architecture, circuit design, and parametric design trade-offs to

meet aggressive technical performance specifications

Perform transistor-level design and simulation using industry leading EDA tools

Lead comprehensive design reviews

• Supervise Analog Circuit Physical Design Layout and edit layouts

• Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test

Engineering and Applications teams to ensure DFT, DFM features and achieve rapid

silicon bring-up and time to production release

• Perform post-layout parasitic-extraction and back-annotated simulations to validate

design

• Perform requisite Monte Carlo Analysis on key circuits to ensure Six-Sigma quality

and yields

• Participate in the bring-up of silicon prototypes

• Initiate Design-of Experiments for Root Cause Analysis, anomalous observations in

silicon across PVT conditions, and propose solutions

Qualifications & Requirements (Education must be included):

• MTech/M.S with minimum 5 years of relevant experience or Ph.D. with 2 years of

Relevant experience in Electrical Engineering

• Provel track record of taking at least one analog-mixed signal part to high-volume

production.•

Proven track record at each stage of the following:

• Circuit architecture development and technical feasibility studies

• Writing detailed block-level specifications and review documents

• Detailed design and simulation of one or more of the following:

Oscillators,

ADCs,

DACs,

temperature sensors,

Integer and Fractional-N PLLs,

Digital PLLs,

low-noise op-amps,

regulators,

bandgap circuits in CMOS.

• Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode

AMS tools, Layout XL

• Extensive knowledge of layout effects for circuit and layout design. Ability to

supervise layout designers

• Extensive experience with post-layout extraction and verifications

• Experience with validation, characterization, qualification, and adherence to

production release criteria

• Ability to communicate and work effectively with geographically dispersed teams of

mixed-signal, digital, verifications engineers

• Ability to work independently and drive solutions to challenging problems

Desired Characteristics & Attributes:

• An “ownership” mind set focusing on the overall success of the business.

• Can do” positive, enthusiastic attitude.

• Demonstrated analytical and problem-solving skills.

• Strong communication skills.

• Ability to work in teams and collaborate effectively with people in different functions.

• Ability to efficiently context – switch between multiple concurrent tasks.

We are a Equal Opportunity Employer.

Contact:

Uday

Mulya Technologies

"Mining The Knowledge Community"

Skills/Experience :

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.

Responsibilities :

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.

Education Requirements :

• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field

Skills/Experience :

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.

Responsibilities :

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.

Education Requirements :

• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field