106 Chip jobs in India

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The Role
The focus of this role in the AECG ASIC organization is to play a key role in driving project success across architecture, design, verification, and physical design. You'll collaborate with cross-functional teams, tackle different problems with diligence for next generation ASICs that meet Engineering, Business and Customer requirements with best PPA.

The Person
The ideal candidate will have a strong interest in Architecture, Digital Logic Design and Verification, Design for Test, Synthesis, Static Timing Analysis, Power Verification and optimization, Physical Design aspects like Floorplan, Full chip timing, Place and Route and Utilization experiments. While we do understand that it is very difficult to have knowledge on expected areas, the candidate should have strong foundation in digital design to pick up the necessary concepts and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or any pre-silicon technical issue. You should be able strike a balance between collaborative problem-solving and independent solution development.

Key Responsibilities

• Study both high-level and micro-architecture specifications to gain an in-depth understanding of new features or changes proposed in new projects.
• Developing micro-architecture specifications and refining execution methodologies for cutting-edge chip designs.
• Work with Architecture/RTL/DFT teams for having optimal design.
• Technical lead on AECG ASIC solutions, tackling problems across domains with focus on driving the best Power, Performance, Area with quality silicon for customers.
• Manage and monitor changes in the given tasks as project matures and be quick to re-align with new or different requirements.
• Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase.
• Work with technology/PD teams to drive signoff margins, reliability related analysis for ASIC use cases.
• Develop technical relationships with broader AMD Design/CAD community and peers.

Preferred Experience

• Strong understanding of development of custom ASICs for external customers.
• Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design.
• Strong understanding of SoC Architecture and Digital Design concepts.
• Strong background in STA, Clocks and Power optimization techniques.
• Experience with Verilog or SystemVerilog and UVM
• Knowledge of power management, boot, CPU, AXI Interconnect and I/O peripherals
• Knowledge of PCIE, JESD, CPRI
• Understanding in physical design for PPA optimization.
• Proven track record of delivering SOCs in process technologies 7nm and below.
• Experience in leading a small team of high performing individuals.

Education & Experience

• Bachelors or Masters degree in in Electrical Engineering or Computer Science. 15+years of experience in ASIC development.

LOCATION:
Bangalore

Benefits offered are described:
AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

We are seeking a highly skilled & motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design execution

Lead multi-block design integration

Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.

Drive IP integration, clocking strategy, power domain definition

Cross-Functional Collaboration

Identify and mitigate design and schedule risks

Engage with external IP vendors, EDA tool providers

Education/Qualification

Required - Bachelor’s in Electrical Engineering, Electronics, or Computer Engineering

Preferred - Master’s or PhD in VLSI Design, Microelectronics, or Computer Architecture

Certifications - Not mandatory, but advanced coursework or certification in SoC design or project management is beneficial

Competence/Certifications

Strong background in:

Digital IC design (RTL to GDSII)

System-level architecture and IP integration

Timing closure (STA) and power-performance-area (PPA) optimization

UPF/CPF for low-power design

Familiarity with design for manufacturability, test (DFT), and silicon debug.

We are seeking a highly skilled & motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design execution

Lead multi-block design integration

Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.

Drive IP integration, clocking strategy, power domain definition

Cross-Functional Collaboration

Identify and mitigate design and schedule risks

Engage with external IP vendors, EDA tool providers

Education/Qualification

Required - Bachelor’s in Electrical Engineering, Electronics, or Computer Engineering

Preferred - Master’s or PhD in VLSI Design, Microelectronics, or Computer Architecture

Certifications - Not mandatory, but advanced coursework or certification in SoC design or project management is beneficial

Competence/Certifications

Strong background in:

Digital IC design (RTL to GDSII)

System-level architecture and IP integration

Timing closure (STA) and power-performance-area (PPA) optimization

UPF/CPF for low-power design

Familiarity with design for manufacturability, test (DFT), and silicon debug.

We are seeking a highly skilled & motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design execution

Lead multi-block design integration

Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.

Drive IP integration, clocking strategy, power domain definition

Cross-Functional Collaboration

Identify and mitigate design and schedule risks

Engage with external IP vendors, EDA tool providers

Education/Qualification

Required - Bachelor’s in Electrical Engineering, Electronics, or Computer Engineering

Preferred - Master’s or PhD in VLSI Design, Microelectronics, or Computer Architecture

Certifications - Not mandatory, but advanced coursework or certification in SoC design or project management is beneficial

Competence/Certifications

Strong background in:

Digital IC design (RTL to GDSII)

System-level architecture and IP integration

Timing closure (STA) and power-performance-area (PPA) optimization

UPF/CPF for low-power design

Familiarity with design for manufacturability, test (DFT), and silicon debug.

We are seeking a highly skilled & motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design execution

Lead multi-block design integration

Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.

Drive IP integration, clocking strategy, power domain definition

Cross-Functional Collaboration

Identify and mitigate design and schedule risks

Engage with external IP vendors, EDA tool providers

Education/Qualification

Required - Bachelor’s in Electrical Engineering, Electronics, or Computer Engineering

Preferred - Master’s or PhD in VLSI Design, Microelectronics, or Computer Architecture

Certifications - Not mandatory, but advanced coursework or certification in SoC design or project management is beneficial

Competence/Certifications

Strong background in:

Digital IC design (RTL to GDSII)

System-level architecture and IP integration

Timing closure (STA) and power-performance-area (PPA) optimization

UPF/CPF for low-power design

Familiarity with design for manufacturability, test (DFT), and silicon debug.

We are seeking a highly skilled & motivated Chip Lead with 15+ years of experience to own the overall chip architecture and design execution

Lead multi-block design integration

Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.

Drive IP integration, clocking strategy, power domain definition

Cross-Functional Collaboration

Identify and mitigate design and schedule risks

Engage with external IP vendors, EDA tool providers

Education/Qualification

Required - Bachelor’s in Electrical Engineering, Electronics, or Computer Engineering

Preferred - Master’s or PhD in VLSI Design, Microelectronics, or Computer Architecture

Certifications - Not mandatory, but advanced coursework or certification in SoC design or project management is beneficial

Competence/Certifications

Strong background in:

Digital IC design (RTL to GDSII)

System-level architecture and IP integration

Timing closure (STA) and power-performance-area (PPA) optimization

UPF/CPF for low-power design

Familiarity with design for manufacturability, test (DFT), and silicon debug.

MPU Engineering team defines and develops System on Chip, ASIC’s, Digital and Analog IP’s for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and network processors.

Responsibilities:

Lead product execution for Automotive/Consumer/Industrial ASIL-B/D SoC’s and Work with architects and systems engineering to define the part. Generate and analyze data to take right and cost-effective architecture decision.

Work with IP, Technology, packaging partners to assess the right IP/packages and technology options for the part.

Work with IP and SoC functions (front end, verification, AMS, DFT, Physical implementation) to understand and resolve inter/intra functional handoff and challenges.

Oversee definition management and make sure the implementation complies with the requirements.

Work closely with downstream team's dependent on SOC, who are working on post-silicon activities, to make sure their needs are addressed.

Work with Program management office for management attention and clearly articulate dependencies and help needed for timely execution of projects.

Assess workload and resource demands based on complexity and create predictable project plans meeting customer requirements.

Cross functional aspects:

This role is primarily about leading cross functional teams:

During part definition is includes a close interaction with Business, Systems, Architects, third party

IP vendors.

During execution a close interaction and decision making is required between Technology,

packaging, IP, Architecture, Various implementation functions, Test and Product Engineering.

Post silicon, close collaboration is needed with Software, Test and production engineering,

Application and Field teams.

Overall, Chip lead is central design point of contact for all cross functional teams associated with

the part.

Job Qualifications:

BE/ B.Tech with 15 years of design development experience, with at least 5 years of leading complete design and/or design functions.

M.Tech/ MS in Electrical Engineering preferred (higher level education may substitute for some

experience).

Experience in leading Global cross functional teams

Experience in leading designs in smaller geometries desired