135 Design Verification Engineer jobs in India

Hi all,

#ACL Digital is Hiring DV Engineers

Experience: 1 - 3 years

• Strong expertise in UVM-based verification.
• Hands-on IP-level verification exposure
• Solid understanding of serial protocols are a must.
• Scripting Language: Perl/Python/TCL

Notice Period: 0–30 Days

Location: Hyderabad/Bangalore

Interested please share profiles at

Thanks,

K Himabindu

Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs.

Key Task: Develop and execute verification plans for complex digital designs.

Methodology: Use UVM/System Verilog to create testbenches, write test cases, and debug failures.

Coverage: Achieve functional and code coverage targets through constrained random and directed testing.

Collaboration: Work with RTL designers to identify and resolve design bugs.

Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug.

Protocols: Verify IP/SoC-level designs for common protocols (AXI, APB, PCIe, DDR, etc.).

Automation: Develop scripts (Python/Perl/TCL) to improve verification efficiency.

Documentation: Maintain verification reports and review results with stakeholders.

Compliance: Ensure adherence to project timelines and quality standards.

Interested, please drop your updated CV to

We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, MAC layer functionality, and RoCE (RDMA over Converged Ethernet). The ideal candidate will have hands-on experience with Synopsys Ethernet PHY and controller IPs , and a strong understanding of high-performance networking technologies.

Key Responsibilities

• Develop and execute verification plans for Ethernet MAC and PHY IP blocks
• Design and implement testbenches using industry-standard methodologies (UVM, SystemVerilog)
• Validate RoCE protocol implementations for low-latency, high-throughput data transfer
• Collaborate with design and architecture teams to ensure functional correctness and performance
• Debug and resolve issues across simulation and emulation platforms
• Contribute to coverage analysis and closure

Preferred Qualifications

• Strong knowledge of Ethernet protocols , including MAC layer operations
• Experience with RoCE (RDMA over Converged Ethernet) and its application in high-speed networking
• Familiarity with Synopsys Ethernet PHY and controller IPs
• Proficiency in SystemVerilog , UVM , and simulation tools (VCS, Questa, etc.)
• Background in ASIC/FPGA design and verification
• Excellent problem-solving and communication skills

Bonus Skills

• Exposure to high-performance computing or data center architectures
• Experience with formal verification or emulation platforms
• Knowledge of PCIe, TCP/IP stack, or other networking protocols

Job Title: Design Verification Engineer

Location: Bangalore, India

Type - Full time

Description:

Client is seeking a Design Verification Engineer. The role is technical, hands-on, in charge of the verification environment for new silicon projects and developments. We are looking for an experienced professional with Passion & Drive to succeed.

Primary Responsibilities Include:

• Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices.
• Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action.
• Overall, responsible for verification of ASIC designs To include such things as:
• Design Verification – Implement test benches in UVM and Sytem
• Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
• Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for
• Debugging Designs for High throughput, Low Latency of Pipeline and
• Dynamic Power Management at full system level.
• Setup Verification Regression suites at RTL Level & Corresponding
• Netlist Level after Synthesis to test any/all Corner case conditions.
• Work closely with Socionext’s design team to ensure the Company is meeting design requirements for projects.
• This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches.
• Work closely with Socionext’s Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timely and accurate deliverables with customers within schedules

Necessary Qualifications:

• BS or MS in Computer Science or Electrical Engineering.
• 5-10+ years of industry experience bringing silicon ICs into high volume production.
• Must have strong experience with UVM.
• Must have a full chip verification experience
• Experience of leading a single project.
• Knowledge of industry standard interfaces. Extensive Familiarity with
• Verilog, Simulation tools & demonstrated ability to debug Problems &
• Troubleshooting in Real Time.
• Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures
• Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification)
• Expertise in writing Perl / Python, awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI,
• SDIO, PCI E & DDR Controllers.
• Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
• Experience with low-level programming of systems in C/C++.
• Experienced in writing scripts in languages such as Perl, Python, and Tcl.
• Functional understanding of constrained random verification process, functional coverage, and code coverage.
• Low power verification UPF
• Team player with excellent communication skills and the desire to take on diverse challenges.
• Customer interaction

Other Qualifications:

• Good knowledge of low power cameras and imaging systems is a plus
• Experience with formal verification tools is a plus.
• CPU Security, Secure boot, Secure JTAG
• Familiarity with ARM architecture
• Familiarity with scripting/programming with Perl/Python, Tcl, C/C++

Experience: 2-3 Years

Location: Hyderabad

Education: B.E./B.Tech. in ECE/EEE

Roles and Responsibilities

1. Strong expertise in UVM-based verification.
2. Hands-on IP-level verification exposure and a solid understanding of serial protocols are a must.

Share resumes at

Hi all,

#ACL Digital is Hiring DV Engineers

Experience: 1 - 3 years

• Strong expertise in UVM-based verification.
• Hands-on IP-level verification exposure
• Solid understanding of serial protocols are a must.

Notice Period: 0–30 Days

Location: Hyderabad/Bangalore

Interested please share profiles at

Thanks,

K Himabindu

VeriFast Technologies is expanding and hiring Sr Verification Engineers in Ahmedabad with minimum 5-8+ years of experience with PCIe/PCI-E or UCIe or CXL or RISC-V with strong SV, UVM and hands on AXI and AHB/APB . Do call me at or drop your CV over to

JOB DESCRIPTION

Title/Position: Design Verification Engineer

Location: Bangalore, Hyderabad, Chennai

Positions: 10

Type: Fulltime

Mail ID:

Key Skills and Responsibilities:

• IP verification Using SV/UVM or SOC Verification using C/SV
• VIP Integration
• Interconnect Protocols: AHB, AXI, APB
• SOC Interfaces: GPIO, SPI, I2C, UART (3+)
• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI or UPF or DDR
• Coverage Closure: Code, Functional and Toggle
• Tools: Synopsys VCS or Cadence Incisive
• Technical Documentation: Testbench Specification, Test Plan Specification
• Good exposure to Scripting skills like Perl or Python or Shell or TCL
• Bachelors in Electronics Engineering is a minimum requirement
• Masters in Electronics or Computer Science Engineering is an added advantage
• 5 to 20 years minimum
• Exposure to working in multi-national environment is required
• Excellent oral and written communication skills is a must.
• An attitude to learn and grow. Adaptability and flexibility are desired.

About us:

Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service

Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless,

Automotive and Embedded Solutions.

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient

turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide,

Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities,

including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from

design to packaged parts. We have a global presence with office locations in the United States, India,

Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in

India, Singapore, Malaysia, Austin, San Jose.

Tessolve offers a highly competitive compensation and benefits along with an electric work environment

to scale one’s intellect, skills and growth.

Disclaimer:

At Tessolve, we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.

Experience: 4-5 Years

Location: Bangalore/Hyderabad

Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics

Roles and Responsibilities

• Verilog, System verilog, UVM
• VHDL, UVVM
• Simulator exposure with VCS, Questa, Xcelium
• Proficient in simulation and HW languages
• Should be able to interpret various LRMs and comply with semantics and testcase creation.

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