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JD:

Analog Circuit Design Engineer:

• 3+ years of experience in one of the following areas.
• Circuit design experience in analog/mixed signal CMOS circuits in High speed Memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc ) or
• Design experience in high-speed analog/mixed-signal blocks for SerDes PHYs such as Rx, CDR, DFE, PI, Tx, PLL, LDO, Comparators, bias generator or experience in - OpAmps, Comparators, Bandgap References, Charge pump, and other analog building blocks or HBM2E SoC analog sub-block design such as DLL, PLL, HBMIO, Clktree, etc.

• Bachelors or Master degree, major in Micro-Electronics, Electronic Engineering or equivalent Ability to work effectively alone or as well as in a team.
• Essential that the individual demonstrates strong communication, verbal and written Requires good communication skills in English.
• Ability to lead a team of junior engineers.

Location: Bangalore

Hi All,

Title:Analog Circuit Design Engineer:

Exp Level:2+yrs

Location: Banglaore

Job Description:

1. B.Tech or M.Tech. in Electronics and Electrical Engineering from an institute of repute.

2. 2 + years of experience in Analog and SERDES IP Circuit Design.

3. The candidate should have relevant experience in following Analog IPs like GPIO, RCOMP, ADC, DAC, LDO, PLL, Thermal Sensor, Voltage Monitor, Process Monitor and their blocks and SERDES IPs i.e. DLL, PLL, Clocking path Analysis, SERDES System Design and Analysis, Power Delivery Analysis, Transmitter (With or without equalization FFE), Receiver (with equalization – CTLE, DFE), Channel Analysis, LDO, RCOMP, Sensors – Process Monitor, Temp Sensor, Voltage Sensor, GPIOs, High Speed View / Test IOs, DFX, High Speed ADC etc.

4. The candidate should have knowledge of one of the following SERDES protocols i.e. DDR IO, UCIe, PCIe, HBMIO, HDMI, MIPI – CDPHY, HDMI etc.

5. The candidate should be well versed with the design tools like Cadence Virtuoso, Spectre / HSpice Simulators, High Speed Simulator APS/XA, Waveform viewer etc.

6. Knowledge and expertise in .lib generation and other views generation will be preferred.

7. Expertise in any scripting language (e.g. PERL, TCL, Python, SKILL) will be also be preferred.

8. The candidate necessarily should have very good communication skills and should be a team player.

9. The candidate should be having problem solving approach and should be able to report blocking issues during the project, as required.

Thanks,

K Himabindu

Title:Analog Circuit Design Engineer:

Exp Level:2+yrs

Location: Banglaore

Job Description:

1. B.Tech or M.Tech. in Electronics and Electrical Engineering from an institute of repute.

2. 2 + years of experience in Analog and SERDES IP Circuit Design.

3. The candidate should have relevant experience in following Analog IPs like GPIO, RCOMP, ADC, DAC, LDO, PLL, Thermal Sensor, Voltage Monitor, Process Monitor and their blocks and SERDES IPs i.e. DLL, PLL, Clocking path Analysis, SERDES System Design and Analysis, Power Delivery Analysis, Transmitter (With or without equalization FFE), Receiver (with equalization – CTLE, DFE), Channel Analysis, LDO, RCOMP, Sensors – Process Monitor, Temp Sensor, Voltage Sensor, GPIOs, High Speed View / Test IOs, DFX, High Speed ADC etc.

4. The candidate should have knowledge of one of the following SERDES protocols i.e. DDR IO, UCIe, PCIe, HBMIO, HDMI, MIPI – CDPHY, HDMI etc.

5. The candidate should be well versed with the design tools like Cadence Virtuoso, Spectre / HSpice Simulators, High Speed Simulator APS/XA, Waveform viewer etc.

6. Knowledge and expertise in .lib generation and other views generation will be preferred.

7. Expertise in any scripting language (e.g. PERL, TCL, Python, SKILL) will be also be preferred.

8. The candidate necessarily should have very good communication skills and should be a team player.

9. The candidate should be having problem solving approach and should be able to report blocking issues during the project, as required.

Interested can share Cv to

AMS Circuit Design Engineer

Experience : 2 to 8 Years.

Location : Hyderabad.

Notice Period : 30 to 60 days.

1. B.Tech or M.Tech. in Electronics and Electrical Engineering from an institute of repute.
2. 2 to 8 years of experience in Analog and SERDES IP Circuit Design.
3. The candidate should have relevant experience in following Analog IPs like GPIO, RCOMP, ADC, DAC, LDO, PLL, Thermal Sensor, Voltage Monitor, Process Monitor and their blocks and SERDES IPs i.e. DLL, PLL, Clocking path Analysis, SERDES System Design and Analysis, Power Delivery Analysis, Transmitter (With or without equalization FFE), Receiver (with equalization – CTLE, DFE), Channel Analysis, LDO, RCOMP, Sensors – Process Monitor, Temp Sensor, Voltage Sensor, GPIOs, High Speed View / Test IOs, DFX, High Speed ADC etc.
4. The candidate should have knowledge of one of the following SERDES protocols i.e. DDR IO, UCIe, PCIe, HBMIO, HDMI, MIPI – CDPHY, HDMI etc.
5. The candidate should be well versed with the design tools like Cadence Virtuoso, Spectre / HSpice Simulators, High Speed Simulator APS/XA, Waveform viewer etc.
6. Knowledge and expertise in .lib generation and other views generation will be preferred.
7. Expertise in any scripting language (e.g. PERL, TCL, Python, SKILL) will be also be preferred.
8. The candidate necessarily should have very good communication skills and should be a team player.
9. The candidate should be having problem solving approach and should be able to report blocking issues during the project, as required.

About Company

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

We are looking for an Architect - Custom Circuit Design for our SLM team in Bengaluru. Does this sound like a good role for you?

• Architect - Custom Circuit Design (R&D engineering team)
• Experience : 10+yrs
• Location: Bengaluru
• BS or MS degree in Electrical Engineering with 10+ years of relevant industry experience.
• Strong Custom Circuit design experience , including specification, circuit design description, and schematics.
• Proficiency with circuit design and simulation tools, IC design CAD packages from any EDA vendor.
• Sound understanding of SPICE simulator concepts and simulation methods.
• Experience with statistical design methodologies like generating and analyzing Monte-Carlo results.
• Technical background in custom design and Standard Cell Design methodologies will be an added advantage

• Job responsibilities:
• Conceptualizing, designing, and productizing state-of-the-art circuit components for SLM monitors realized through ASIC design flow.
• Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics.
• Developing statistical simulation methodologies and collaborating with the layout team to achieve optimal design solutions.
• Characterizing designed custom cells and deploying new circuits into test chips for post-silicon characterization.
• Creating new cells and updating existing ones through collaboration with architects and Physical Design engineers.
• Conducting pre and post-layout simulations and characterizations across various design corners to ensure reliability and aging requirements.

Please share your updated CV to or refer who would like to explore this opportunity.

• Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

Position Overview

We are seeking a highly experienced Analog Circuit Design Technical Lead with 15+ years of proven expertise in the design, development, and productization of advanced analog and mixed-signal IPs for high-performance semiconductor solutions. The candidate will be responsible for Analog Design , driving innovation, ensuring robust design execution, and collaborating with cross-functional teams to deliver state-of-the-art silicon.

Key Responsibilities

• Technical Leadership
• Lead and mentor the analog design team, providing architectural, circuit-level, and system-level guidance.
• Drive innovation in high-speed and low-power analog design for cutting-edge SoCs.
• Define design methodologies, best practices, and ensure technical excellence across the team.
• Design Ownership
• Lead the design and development of analog IPs such as SerDes (PAM4/NRZ), ADCs, DACs, PLLs, LDOs, CDRs, Tx/Rx front-ends, clock/data recovery circuits , and other high-performance analog building blocks.
• Oversee schematic design, transistor-level simulations, layout, parasitic extraction, and verification.
• Guide architecture trade-offs to balance performance, power, area, and manufacturability.
• Cross-functional Collaboration
• Work closely with digital design, verification, system, packaging, and technology teams to ensure seamless integration of analog IPs into SoCs.
• Partner with foundries and EDA vendors to leverage advanced process technologies (FinFET, advanced CMOS, etc.).
• Project Execution
• Own the analog design project execution cycle from feasibility study to silicon validation.
• Drive technical reviews, design sign-offs, and ensure first-pass silicon success.
• Contribute to IP and SoC-level bring-up, debug, and validation.
• Innovation & Roadmap
• Keep abreast of industry trends in high-speed interfaces (e.g., PCIe, Ethernet, GMSL/ASA, USB, DDR) and contribute to technology roadmap definition.
• Drive continuous improvement in analog/mixed-signal design methodologies, flow automation, and productivity.

Required Qualifications

• Experience: 15+ years in analog/mixed-signal IC design, with a track record of successful silicon delivery in advanced process nodes.
• Technical Depth:
• Expertise in design of high-speed SerDes (NRZ, PAM4) , ADCs/DACs (high-speed, high-resolution) , PLLs/DLLs , CTLEs , CDRs , LDOs , and other analog building blocks.
• Strong knowledge of signal integrity, jitter analysis, noise coupling, and layout considerations .
• Hands-on experience with Spectre, HSPICE, Verilog-A/MS, and other circuit simulators .
• Solid understanding of system-level trade-offs (BER, jitter tolerance, channel modeling, equalization techniques, PAM4 signaling) .
• Leadership: Proven ability to lead, mentor, and grow high-performing analog design teams.
• Process Knowledge: Experience with FinFET and advanced CMOS nodes (e.g., 28nm, 16nm, 7nm, and below) .
• Education: Master’s or PhD in Electrical Engineering (Analog/Mixed-Signal specialization preferred).

Preferred Skills

• Experience with automotive-grade (AEC-Q100) and functional safety (ISO 26262) requirements .
• Exposure to EDA flow automation, machine learning for circuit optimization, or custom design methodologies .
• Strong publication/patent record in analog/mixed-signal design.
• Excellent communication, cross-site collaboration, and stakeholder management skills.

Why Join Us

• Opportunity to be a part of and shape a world-class analog design team .
• Work on cutting-edge technologies in automotive and high-speed connectivity .
• Be a key contributor to the success of next-generation semiconductor products

JD:

Analog Circuit Design Engineer:

• 3+ years of experience in one of the following areas.
• Circuit design experience in analog/mixed signal CMOS circuits in High speed Memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc ) or
• Design experience in high-speed analog/mixed-signal blocks for SerDes PHYs such as Rx, CDR, DFE, PI, Tx, PLL, LDO, Comparators, bias generator or experience in - OpAmps, Comparators, Bandgap References, Charge pump, and other analog building blocks or HBM2E SoC analog sub-block design such as DLL, PLL, HBMIO, Clktree, etc.

• Bachelors or Master degree, major in Micro-Electronics, Electronic Engineering or equivalent Ability to work effectively alone or as well as in a team.
• Essential that the individual demonstrates strong communication, verbal and written Requires good communication skills in English.
• Ability to lead a team of junior engineers.

Location: Bangalore

EDA Flow Developer

We are seeking an experienced IR & EM Technology Expert to join our Flow Development Team. The successful candidate will have a strong background in CAD design and a deep understanding of IR & EM technology. This is an excellent opportunity for a motivated individual to contribute to the development of cutting-edge Flows, ensuring the highest level of performance, power efficiency, and reliability.

Location: Bangalore

Job Description

In your new role you will:

• Design and develop Flows for IR and EM technology-based solutions for ASIC designs, focusing on signal integrity, power integrity, and thermal management.
• Collaborate with cross-functional teams, including architecture, design, and verification, to ensure seamless integration of IR and EM technology into central flow
• Develop and maintain IR and EM scripts, and tools to support ASIC design flows.
• Perform IR and EM analysis, simulation, and verification to ensure compliance with design specifications and industry standards.
• Optimize IR and EM performance, power consumption, and area usage for ASIC designs.
• Stay up-to-date with the latest advancements in IR and EM technology, EDA tools, and industry trends, applying this knowledge to improve design methodologies and flows.
• Develop and maintain documentation, including design guides, user manuals, and technical reports.

Your Profile

You are best equipped for this task if you have:

• 4-8 years of experience in Flow Development, with a focus on IR and EM technology in ASIC design.
• Bachelor's or Master's degree in electrical engineering, Computer Engineering, or a related field.
• Proficiency in RedHawk-SC, RedHawk, Voltus or similar EDA tools for IR/EM which are industry standard.
• Excellent problem-solving skills, with the ability to analyze complex technical issues and develop creative solutions.
• Effective communication and collaboration skills, with the ability to work with cross-functional teams and stakeholders.
• Strong documentation and reporting skills, with the ability to create clear, concise technical documents.
• Coding skills using Python

Nice to Have:

• Experience with scripting languages, such as Python, Perl, or Tcl.
• Any Data management tools such as Git, Perforce, clearcase

ASIC Design Engineer

Location: Hyderabad

Experience: 5–10 years

Job Description

Key Responsibilities:

• Develop and implement RTL design for complex ASIC SoCs/IPs .
• Work on micro-architecture design, coding (Verilog/SystemVerilog ), and RTL integration .
• Perform design synthesis , lint , CDC/RDC checks, and timing closure.
• Collaborate with verification, physical design, and architecture teams to ensure first-pass silicon success.
• Debug design issues at block and SoC level, support verification and post-silicon validation.
• Contribute to low-power , high-performance design techniques for advanced technology nodes.

Required Skills:

• Strong expertise in RTL design using Verilog/SystemVerilog.
• Hands-on experience with ASIC flow: synthesis, STA , constraints , ECO .
• Knowledge of standard protocols (AXI, AHB, PCIe, DDR, Ethernet , etc.).
• Familiarity with power intent (UPF/CPF ) and clock /power domain crossings.
• Experience in working with EDA tools (Synopsys /Cadence /Mentor ).
• Good problem-solving and debugging skills.

About Company

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.