253 Layout Engineer jobs in India

Job Title: Layout Engineer –

Job Summary

We are hiring a Layout Engineer who is skilled in BIM and Revit with 3D modeling experience. The person will work on layout development, clash coordination, and drawing documentation for Baggage Handling. You should have at least 3 years of hands-on Revit modeling experience, be able to coordinate with other disciplines, and support the team in intermediate Revit problem-solving. Conveyor system knowledge is a plus but not a must.

Key Responsibilities

System & Layout Design

Review and optimize system layouts during sales and engineering phases mainly using Revit.

Create basic Revit models using functional design inputs.

Integrate safety, ergonomics, and accessibility into layouts.

Coordinate interfaces with buildings, operators, equipment, and procurement.

3D Modeling, 2D Drafting & Documentation

Create and manage 3D conveyor models in Revit based on design inputs and extract 2D drawings.

Perform basic clash detection using Navisworks and maintain documentation and drawing consistency

Incorporate functional attributes and prepare equipment specifications.

Continuous Improvement & Knowledge Sharing

Willing to learn new things and adapt to change quickly.

Should take responsibility in work and share knowledge when needed by colleagues.

Preferred Qualifications

Bachelor’s degree in mechanical engineering or related field.

3–5 year’s experience in Revit modeling and layout development.

Must be proficient in Revit and basic BIM workflows.

Key Competencies

Technical Skills

Intermediate proficiency in AutoCAD (3D modeling and 2D drafting)

Intermediate proficiency in Revit, Navis Works, BIM Documentation and Work Flow

Familiar with clash detection and resolving simple issues

Conveyor/mechanical system design expertise

Layout planning and specification writing

Understanding of engineering processes

System Integration

Coordination across mechanical, electrical, and controls disciplines

Interface understanding (building, operator, procurement)

Project Execution

Work breakdown and prioritization

Change/risk management and site readiness

Execute tasks as assigned in a structured project environment

Communication & Collaboration

Proficient in written and spoken English

Shares issues and updates clearly

Works well with others in a multidisciplinary team

Quality & Safety

Design for safety, ergonomics, and standards compliance

Should be able to understand and follow the quality checks

Continuous Improvement

Analytical thinking and problem-solving

Contributor to improving processes, tools and templates as part of continuous improvement.

Knowledge transfer and Mentoring colleagues.

Soft Skills Requirements

Communication

Clear, structured communication

Ability to explain technical concepts to non-technical audiences

Collaboration

Strong team player across multidisciplinary teams

Supports colleagues

Leadership & Ownership

Takes initiative, leads assigned tasks

Problem Solving

Analytical mindset and solutions-oriented under pressure

Adaptability

Manages changing priorities and dynamic work environments

Attention to Detail

Maintains high quality and accuracy in designs and modeling.

Time Management

Delivers on time, multitasks effectively

Job Title: Layout Engineer –

Job Summary

We are hiring a Layout Engineer who is skilled in BIM and Revit with 3D modeling experience. The person will work on layout development, clash coordination, and drawing documentation for Baggage Handling. You should have at least 3 years of hands-on Revit modeling experience, be able to coordinate with other disciplines, and support the team in intermediate Revit problem-solving. Conveyor system knowledge is a plus but not a must.

Key Responsibilities

System & Layout Design

Review and optimize system layouts during sales and engineering phases mainly using Revit.

Create basic Revit models using functional design inputs.

Integrate safety, ergonomics, and accessibility into layouts.

Coordinate interfaces with buildings, operators, equipment, and procurement.

3D Modeling, 2D Drafting & Documentation

Create and manage 3D conveyor models in Revit based on design inputs and extract 2D drawings.

Perform basic clash detection using Navisworks and maintain documentation and drawing consistency

Incorporate functional attributes and prepare equipment specifications.

Continuous Improvement & Knowledge Sharing

Willing to learn new things and adapt to change quickly.

Should take responsibility in work and share knowledge when needed by colleagues.

Preferred Qualifications

Bachelor’s degree in mechanical engineering or related field.

3–5 year’s experience in Revit modeling and layout development.

Must be proficient in Revit and basic BIM workflows.

Key Competencies

Technical Skills

Intermediate proficiency in AutoCAD (3D modeling and 2D drafting)

Intermediate proficiency in Revit, Navis Works, BIM Documentation and Work Flow

Familiar with clash detection and resolving simple issues

Conveyor/mechanical system design expertise

Layout planning and specification writing

Understanding of engineering processes

System Integration

Coordination across mechanical, electrical, and controls disciplines

Interface understanding (building, operator, procurement)

Project Execution

Work breakdown and prioritization

Change/risk management and site readiness

Execute tasks as assigned in a structured project environment

Communication & Collaboration

Proficient in written and spoken English

Shares issues and updates clearly

Works well with others in a multidisciplinary team

Quality & Safety

Design for safety, ergonomics, and standards compliance

Should be able to understand and follow the quality checks

Continuous Improvement

Analytical thinking and problem-solving

Contributor to improving processes, tools and templates as part of continuous improvement.

Knowledge transfer and Mentoring colleagues.

Soft Skills Requirements

Communication

Clear, structured communication

Ability to explain technical concepts to non-technical audiences

Collaboration

Strong team player across multidisciplinary teams

Supports colleagues

Leadership & Ownership

Takes initiative, leads assigned tasks

Problem Solving

Analytical mindset and solutions-oriented under pressure

Adaptability

Manages changing priorities and dynamic work environments

Attention to Detail

Maintains high quality and accuracy in designs and modeling.

Time Management

Delivers on time, multitasks effectively

Job Title:

Memory Layout Engineer

Location : Bangalore

Experience Required:

3–5 years in custom layout design of memory circuits (SRAM, eDRAM, ROM, Register Files, CAM, or emerging memories).

Job Summary:

We are seeking a Memory Layout Engineer with strong expertise in custom layout design of memory macros at advanced technology nodes. The candidate will be responsible for creating high-quality, DRC/LVS clean layouts, ensuring matching, density, reliability, and performance optimization, and working closely with circuit design and verification teams to deliver robust memory IPs.

Key Responsibilities:

• Develop full-custom layout for memory circuits (SRAM, ROM, Register File, CAM, etc.) at block and macro levels .
• Perform floorplanning, placement, routing, and optimization for area, performance, and power .
• Ensure DRC, LVS, ERC, and antenna-clean layouts across different process corners .
• Implement matching techniques, shielding, dummy structures, and guard rings for robust design .
• Work on memory bitcell arrays, periphery circuits, sense amplifiers, decoders, and write drivers .
• Perform parasitic extraction (PEX) and layout-dependent effect (LDE ) analysis.
• Collaborate with circuit designers, verification engineers, and CAD teams for integration and validation.
• Support signoff and tapeout with foundry-specific requirements.
• Automate layout generation or checks using SKILL, Python, or TCL scripting (if applicable).

Required Skills & Qualifications:

• 3–5 years of hands-on experience in custom layout of memory IPs .
• Proficiency in EDA tools (Cadence Virtuoso, Synopsys Custom Compiler, Mentor Graphics).
• Strong knowledge of advanced CMOS processes (28nm, 16nm, 7nm, FinFET, etc.).
• Experience in layout methodologies for high-density and high-performance memory arrays.
• Solid understanding of DRC/LVS/ERC/ANT/PEX signoff flows.
• Knowledge of parasitics impact on memory performance.
• Familiarity with reliability requirements (electromigration, IR drop, ESD).
• Good problem-solving and debugging skills.

Preferred Skills:

• Exposure to SRAM compilers or memory automation flows.
• Knowledge of low-power design techniques in memories.
• Experience with EM/IR analysis tools.
• Familiarity with yield and variability considerations in memory design.

Educational Qualification:

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related fields.

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.

• Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.

• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.

• Responsible for on-time delivery of block-level layouts with acceptable quality.

• Excellent problem-solving skills in physical verification of custom layout.

• Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment.

• Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.

• Contribute to effective project-management.

• Effectively communicating with Local engineering teams to assure the success of layout project.

Educational Background

• BE or MTech in Electronic/VLSI Engineering

• 5 + year experience in analog/custom layout design in advanced CMOS process.

Job Title:

Memory Layout Engineer

Location : Bangalore

Experience Required:

3–5 years in custom layout design of memory circuits (SRAM, eDRAM, ROM, Register Files, CAM, or emerging memories).

Job Summary:

We are seeking a Memory Layout Engineer with strong expertise in custom layout design of memory macros at advanced technology nodes. The candidate will be responsible for creating high-quality, DRC/LVS clean layouts, ensuring matching, density, reliability, and performance optimization, and working closely with circuit design and verification teams to deliver robust memory IPs.

Key Responsibilities:

• Develop full-custom layout for memory circuits (SRAM, ROM, Register File, CAM, etc.) at block and macro levels.
• Perform floorplanning, placement, routing, and optimization for area, performance, and power.
• Ensure DRC, LVS, ERC, and antenna-clean layouts across different process corners.
• Implement matching techniques, shielding, dummy structures, and guard rings for robust design.
• Work on memory bitcell arrays, periphery circuits, sense amplifiers, decoders, and write drivers.
• Perform parasitic extraction (PEX) and layout-dependent effect (LDE) analysis.
• Collaborate with circuit designers, verification engineers, and CAD teams for integration and validation.
• Support signoff and tapeout with foundry-specific requirements.
• Automate layout generation or checks using SKILL, Python, or TCL scripting (if applicable).

Required Skills & Qualifications:

• 3–5 years of hands-on experience in custom layout of memory IPs.
• Proficiency in EDA tools (Cadence Virtuoso, Synopsys Custom Compiler, Mentor Graphics).
• Strong knowledge of advanced CMOS processes (28nm, 16nm, 7nm, FinFET, etc.).
• Experience in layout methodologies for high-density and high-performance memory arrays.
• Solid understanding of DRC/LVS/ERC/ANT/PEX signoff flows.
• Knowledge of parasitics impact on memory performance.
• Familiarity with reliability requirements (electromigration, IR drop, ESD).
• Good problem-solving and debugging skills.

Preferred Skills:

• Exposure to SRAM compilers or memory automation flows.
• Knowledge of low-power design techniques in memories.
• Experience with EM/IR analysis tools.
• Familiarity with yield and variability considerations in memory design.

Educational Qualification:

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related fields.

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.

• Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.

• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.

• Responsible for on-time delivery of block-level layouts with acceptable quality.

• Excellent problem-solving skills in physical verification of custom layout.

• Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment.

• Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.

• Contribute to effective project-management.

• Effectively communicating with Local engineering teams to assure the success of layout project.

Educational Background

• BE or MTech in Electronic/VLSI Engineering

• 5 + year experience in analog/custom layout design in advanced CMOS process.