44 Layout Engineer jobs in India

Hi All,

Title : Analog Layout Engineer

Exp Level:3+ yrs

Location: Bangalore

Job Description:

Design and development of full custom analog/mixed-signal layout at block and top level.

Strong expertise in analog layout techniques for circuits such as ADC, DAC, PLL, LDO, Bandgap, etc.

Hands-on experience with layout tools like Cadence Virtuoso, Calibre, and Mentor tools.

Ensure layout meets DRC, LVS, ERC, Antenna, and other physical verification requirements.

Work closely with circuit design engineers to plan, review, and optimize layout.

Experience in advanced process nodes (e.g., 7nm, 5nm, 3nm) preferred.

Understanding of EMIR, ESD, and reliability requirements

Proficient in hierarchical and flat layout methodologies.

Good knowledge of parasitic extraction and optimization.

Ability to handle tight schedules and complex designs independently.

Experience working in ODC/remote team model is a plus

Strong communication and documentation skills.

Commitment to high quality and first-pass success.

Interested can share Cv to

Thanks,

K Himabindu

ACL Digital is looking for smart and enterprising Memory Layout Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.

Experience: 4 to 5 Years

Skills :

• Having lower node Finfet experience. (10nm & less)
• Memory compiler layout, SRAM, Register File (RF)
• Available to join in 3-4 weeks .
• Location: Noida/ Hyderabad

For more details Contact:

Email:

Job Title: Memory Layout Engineer

Experience: 3+yrs

Location: Bangalore

Job Type: Full-time

Industry: Semiconductors / VLSI / Memory Design

Job Summary:

We are looking for a Memory Layout Engineer with strong expertise in physical layout design of memory components such as SRAM, ROM, Register Files, or custom memory IPs. The candidate will be responsible for delivering high-quality, DRC/LVS-clean layouts optimized for performance, area, and power.

Key Responsibilities:

• Design full-custom layouts for memory components like SRAM, ROM, CAM, Register Files, or sense amplifiers.
• Work closely with circuit designers to understand schematics and translate them into optimized layouts.
• Floorplanning, transistor-level placement, routing, and matching to meet electrical and physical design constraints.
• Run physical verification (DRC, LVS, ERC, antenna checks) using industry-standard tools.
• Perform parasitic extraction (PEX) and assist in post-layout simulation.
• Ensure layouts meet design rules for process technologies (e.g., 5nm, 7nm, 16nm, 28nm).
• Implement design automation using SKILL, Python, or Tcl where applicable.
• Work with cross-functional teams (circuit, verification, CAD) to meet project milestones.

Required Skills and Experience:

• B.E/B.Tech or M.E/M.Tech in Electronics or Electrical Engineering.
• 3 years of hands-on experience in custom layout design, preferably in memory design.
• Strong understanding of CMOS layout techniques, matching, shielding, and electromigration.
• Experience with:
• Tools: Cadence Virtuoso, Calibre DRC/LVS, StarRC, ICC, QRC
• Technologies: Advanced FinFET and planar nodes (28nm and below)
• Deep understanding of design rules (DRC), LVS, and physical verification sign-off flows.
• Excellent attention to detail, layout quality, and debugging skills.

Preferred Qualifications:

• Experience in compiler-based memory generation or memory compilers.
• Exposure to high-speed or low-power memory layout optimization techniques.
• Experience working with foundry design kits (PDKs) and tape-out processes.
• Scripting experience in SKILL or Python for layout automation and checks.

Why Join Us?

• Work on next-generation memory designs for AI, mobile, and high-performance computing chips.
• Be part of a highly skilled layout team with access to leading-edge nodes and tools.
• Competitive salary, performance bonuses, and long-term growth opportunities.

Interested can share Cv to

Job Title: IO Layout Engineer

Experience: 3+ Years

Location: Bangalore

Employment Type: Full-time

Industry: Semiconductors / ASIC / VLSI / IO & ESD Design

Job Summary:

We are looking for a highly motivated and experienced IO Layout Engineer to join our custom layout team. The candidate will be responsible for full-custom layout of IO cells, ESD protection structures, and high-voltage interfaces for ASIC/SoC applications in deep submicron and FinFET technologies.

Key Responsibilities:

• Perform transistor-level custom layout of various types of IO cells including:
• Standard IOs (CMOS, LVTTL, LVCMOS, SSTL, HSTL)
• High-speed and specialty IOs (DDR, USB, PCIe, HDMI, etc.)
• ESD structures, pad rings, and protection circuits
• Work closely with IO circuit designers to interpret schematics and design intent.
• Ensure robust layout practices for:
• ESD compliance
• Latch-up prevention
• Electromigration (EM)
• Voltage isolation and guard ring planning
• Ensure layout meets foundry-specific DRC, LVS, and antenna rules.
• Run and close physical verification (DRC, LVS, ERC, ANT) using industry-standard tools.
• Participate in floorplanning of IO ring and integration with analog/digital blocks.
• Coordinate with packaging, ESD, and reliability teams to support silicon tapeout.

Required Skills and Experience:

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI.
• 3+ years of hands-on experience in IO and/or ESD layout.
• Strong understanding of ESD protection concepts and latch-up avoidance.
• Expertise in Cadence Virtuoso for layout design and implementation.
• Experience with DRC/LVS tools (Calibre, Assura, PVS).
• Familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.).
• Good knowledge of layout-dependent effects (LDE), IR drop, and reliability constraints.
• Attention to detail and strong debugging/problem-solving skills.

Preferred Qualifications:

• Experience in high-voltage or multi-voltage IO layout (1.8V/3.3V/5V interfaces).
• Experience with IO ring planning and integration in complex SoC floorplans.
• Familiarity with power grid design, bump/ball map coordination, and ESD co-design.
• Scripting experience in SKILL, Tcl, or Python for layout automation.

Interested can share Cv to

ACL Digital is looking for smart and enterprising Memory Layout Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.

Experience: 4 to 5 Years

Skills :

1. Having lower node Finfet experience. (10nm & less)
2. Memory compiler layout, SRAM, Register File (RF)
3. Available to join in 3-4 weeks .
4. Location: Noida/ Hyderabad

For more details Contact:

Email:

• Experience : 3 to 8 years
• Location : Hyderabad/Noida

Role and Responsibilities:

• Responsible for Memory Compiler layout development and verification.·
• Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·
• Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.· Responsible for on-time delivery of block-level layouts with acceptable quality.· Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.·
• Guide junior team-members in their execution of Sub block-level layouts & review their work.·
• Contribute to effective project-management.·
• Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Qualification/ Requirements:

• Should be well familiar with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders.·
• Should have expertise in floor planning, power planning, block area estimation of memory designs or compliers.·
• Should be able to perform leaf cell layout development and physical verification.·
• Should have adequate knowledge of schematics, interface with circuit designer and CAD and process development team.·
• Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.·
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,· Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.·
• Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.·
• Should have leadership qualities and able to do multi-tasking as required.·
• Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.·

• Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
• Knowledge of Skill coding and layout automation is a plus.

Analog Layout Engineer

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering , Computer Engineering , or a related field.
• 4+ years of experience in analog layout design with a focus on TSMC 7nm , 5nm , and 3nm process technologies.
• Proficiency with Cadence Virtuoso , Mentor Graphics , Synopsys IC Compiler , or equivalent analog layout tools.
• Hands-on experience with TSMC PDKs and process technologies for 7nm , 5nm , and 3nm nodes.
• Strong knowledge of analog circuit design principles , including transistor-level design , biasing , signal integrity , and noise analysis .
• Extensive experience with DRC , LVS , parasitic extraction , and layout verification using tools such as Calibre and ICValidator .
• In-depth knowledge of FinFET , SOI , and other advanced semiconductor process technologies at sub-7nm nodes.
• Ability to optimize analog layouts for PPA (performance, power, area) .
• Experience with low-power design techniques in advanced process nodes .
• Familiarity with high-performance analog designs and layouts in 7nm , 5nm , and 3nm technologies.
• Strong problem-solving skills and ability to troubleshoot and resolve layout issues.

Preferred Qualifications:

• Experience with mixed-signal layouts (analog and digital) for full-chip designs .
• Familiarity with RF layout techniques for high-frequency analog circuits.
• Experience in working with multiple layout design environments (e.g., Virtuoso , IC Studio , Synopsys Custom Compiler ).
• Knowledge of electromagnetic interference (EMI) , signal integrity , and high-speed layout techniques in advanced nodes.
• Exposure to full-custom layout techniques for complex analog IC designs .
• Understanding of advanced packaging technologies and their impact on analog layout design.
• Experience with statistical analysis tools for yield and design optimization.

Location: Bangalore

Experience: 4 to 8 Years

ACL Digital is looking for a

1.Memory Layout Engineer with 2+ years of Exp for Noida

2.Memory Design Engineer with 2+ years of Exp for Noida

Interested share cv to

Exp level: 2 to 5 years

Location: Bangalore

Notice Period: Immediate joiners are preffered.

Responsibilites:

• Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCs, DACs, voltage regulators) using TSMC 3nm and 5nm nodes.
• Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) to ensure design compliance.

Required Skills:

• Strong experience in analog layout design at advanced nodes (TSMC 3nm and 5nm).
• Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar.
• Understanding of layout-dependent effects (LDE) and its impact on performance.
• Knowledge of parasitic extraction, simulation, and optimization.
• Familiarity with design for manufacturability (DFM) techniques.

Please email Resumes to