457 Rtl Design Engineer jobs in India

Job Title: RTL Design Engineers

Exp Level: 4+ yrs

Loctaion: Hyderabad /Bangalore

Job Description:

• RTL coding knowledge

• Top-level (SOC) level basic industry standard Arch knowledge

• SoC & IP level Integration knowledge

• IPXACT knowledge

• IORING and Phys & GPIOs basic functionality

• Design Partitioning(Tilification) knowledge

• Design RTL quality checks:

• Clock domain crossing(CDC)
• Reset domain crossing(RDC)
• LINT
• VSI
• UPF knowledge
• LEC(Logic equivalence check)
• Timing concepts & SDC knowledge

• Tools knowledge:

• Vc_static or equivalent other tools(VSI)
• VC_spyglass LINT, CDC and RDC
• 0in
• Formality and conformal LEC tool

• Design and scripting languages:

• Verilog and SV
• Perl
• Python
• TCL

RTL Design Engineer

Experience : 2-3 years

Location : Hyderabad

Knowledge in RTL Coding in Verilog or VHDL

Strong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc.

Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc.

Good Knowledge in Tcl, Python scripting

Interested,please drop your updated resume to

Hi All,

Job Title - RTL Design Engineers

Exp Level: 4+ yrs

Loctaion: Hyderabad

Job Description:

• RTL coding knowledge

• Top-level (SOC) level basic industry standard Arch knowledge

• SoC & IP level Integration knowledge

• IPXACT knowledge

• IORING and Phys & GPIOs basic functionality

• Design Partitioning(Tilification) knowledge

• Design RTL quality checks:

Clock domain crossing(CDC)

Reset domain crossing(RDC)

LINT

VSI

UPF knowledge

LEC(Logic equivalence check)

Timing concepts & SDC knowledge

• Tools knowledge:

Vc_static or equivalent other tools(VSI)

VC_spyglass LINT, CDC and RDC

0in

Formality and conformal LEC tool

• Design and scripting languages:

Verilog and SV

Perl

Python

TCL

Thanks,

K Himabindu

Principal RTL Design Engineer & Architect

Bangalore

We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in leading state of the RTL designs involving solutions for automotive camera and display systems.

Responsibilities

• Design and develop microarchitectures for a set of chips involving MIPI CSI,DSI and SerDes protocols

• Microarchitecture and RTL coding ensuring optimal performance, power, area

• Collaborate with software teams to define configuration requirements, verification collaterals etc.

• Work with verification teams on assertions, test plans, debug, coverage etc.

Qualifications and Preferred Skills

• BTech, MTech in ECE/EE

• 10+ years hands-on experience in microarchitecture and RTL development

• Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface

• In-depth understanding of MIPI CSI and DSI protocols

• Experience designing IP blocks for video and audio design

Proficiency in Verilog, System Verilog

• Familiarity with industry-standard EDA tools and methodologies

• Experience with large high-speed, pipelined, and low power designs

• Excellent problem-solving skills and attention to detail

• Strong communication and collaboration skills

• Experience with modern programming languages like Python is a plus

Job Title: RTL Design Engineers

Exp Level: 4+ yrs

Loctaion: Hyderabad

Job Description:

• RTL coding knowledge

• Top-level (SOC) level basic industry standard Arch knowledge

• SoC & IP level Integration knowledge

• IPXACT knowledge

• IORING and Phys & GPIOs basic functionality

• Design Partitioning(Tilification) knowledge

• Design RTL quality checks:

• Clock domain crossing(CDC)
• Reset domain crossing(RDC)
• LINT
• VSI
• UPF knowledge
• LEC(Logic equivalence check)
• Timing concepts & SDC knowledge

• Tools knowledge:

• Vc_static or equivalent other tools(VSI)
• VC_spyglass LINT, CDC and RDC
• 0in
• Formality and conformal LEC tool

• Design and scripting languages:

• Verilog and SV
• Perl
• Python
• TCL

Experience Level:5+ years of RTL design and development

Location: Hyderabad/Bangalore

Job Description:Silicon Design Engineer

Basic Job Deliverable:Silicon Design Engineer (RTL Design and Development)

o Responsible for RTL design and development

o Responsible for generating documents, such as requirements specification, design, user-guide, etc.,

o Experience:

 Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools

Experience with Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies

xperience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc.

 ong debugging skills at device and board level

cripting language experience like Perl, Python or TCL

xcellent interpersonal, written and verbal communication skills

xcellent communication, problem solving and analytical skills

Qualification:B.Tech/M.Tech (CSE/ECE/EEE)

Interested can share CV to

Job Responsibility:

• Drive architecture definition in conjunction with the Systems Architects, and working with the cross function Design, Verification, Validation and supporting SW/FW teams.
• Own the complete design of one or more cutting edge digital IPs from specification to final design delivery
• Deliver IP with first time right quality, ensuring best in class KPIs and performance
• Contribute to continuous methodology developments to improve the speed and reliability of IP execution, and the critical KPIs
• Ensure proper documentation of IP design specifications, and release checks

Job Qualification:

• BSEE required, MSEE preferred with 7+ years of industry related experience
• Must have experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies
• Self-driven and capable for independent work and independent decision making.
• Fluency in design & verification languages such as VHDL, Verilog, C and System Verilog.
• Knowledge on Verification Methodologies to actively participate in Debug Analysis
• Prior experience in developing foundation IPs and differentiating/market-oriented IPs
• Excellent written and verbal communication skill.

Experience : 4+years

Location : Bangalore

Job Description:

• Candidate should be good in Integration of SOC & RTL coding.
• Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.
• Should be aware of scripting language.
• Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.
• Should have good understanding of SoC flows.

Primary Skills

• VHDL, Verilog, Micro-architecture, RTL coding, CDC, Lint, Synthesis, STA, IP development, SoC integration, VCLP, scripting - Perl, Python, Shell, and Tcl.

Secondary Skills

• Synopsis/Cadence tool flow, ARM Coretex, DMA, DDR, SPI, I2C, UART, AHB/AXI/APB, Ethernet, USB, PCIe, Mipi CSI/DSI, LPDDR.

Position: RTL Design Engineer

Experience: 5 - 8 Years

Qualifications: BE/Btech in ECE/EEE

Responsibilities -

• The candidate should have strong RTL design experience.
• Strong design experience in Ethernet IPs or Ethernet protocol domain.
• Knowledge in Verilog/VHDL languages
• Scripting languages: TCL/Perl/Python (any one).
• Knowledge of AXI Protocols.