30 Specific jobs in India

HRBP - Program Specific Services

JOB ROLE

Work Location: Kozhikode

The HRBP - Program-Specific Services is responsible for delivering HR support, strategic guidance, and engagement initiatives for the Xylem Commerce Program, Non-Residential Program, and Government Exams Program. This role requires close collaboration with program leaders to ensure alignment with HR best practices, focusing on employee engagement, performance management, compliance, and recruitment. The HRBP will work to create a positive work environment for staff across these distinct programs, ensuring that HR policies and practices meet the unique needs of each program.

Duties & Responsibilities.

1.HR Support for Program-Specific Services: Serve as the primary HR contact for employees in the Commerce, Non-Residential, and Government Exams programs. O Provide guidance on HR policies and practices, adapting them to the specific requirements and challenges of each program. O Collaborate with program leaders to align HR strategies with program goals and objectives.

2.Talent Acquisition & Onboarding : O Work with the Talent Acquisition team to develop recruitment strategies for program specific roles, ensuring a steady pipeline of qualified candidates. O Oversee the onboarding process for new hires in each program, ensuring a smooth and engaging experience that fosters alignment with program goals. O Conduct orientation sessions tailored to each program, introducing new hires to key expectations, team dynamics, and culture.

3.Employee Relations & Engagement : O Address employee relations issues within the programs, including managing grievances, resolving conflicts, and fostering open communication. O Develop and implement engagement activities tailored to each program to boost employee morale and commitment. O Conduct regular feedback sessions and check-ins with employees to monitor engagement levels and gather insights on program-specific concerns.

4.Performance Management & Development : O Partner with program leaders to facilitate goal setting, performance appraisals, and continuous feedback for staff in each program. O Identify high-potential employees and work with managers to create personalized development plans that align with career growth and program objectives. O Support managers in addressing underperformance through coaching and performance improvement plans (PIPs).

5.Learning & Development (L&D) Initiatives : O Assess training needs within each program and coordinate with the L&D team to design and deliver relevant training programs. O Promote participation in L&D programs and encourage managers to support ongoing employee development. O Track training participation and gather feedback to assess the impact of L&D initiatives on employee performance and satisfaction.

6.Compliance & Policy Implementation: O Ensure all HR practices within the Commerce, Non-Residential, and Government Exams programs comply with organizational policies and local labor laws. O Provide regular updates to staff on HR policies, procedures, and compliance requirements. O Conduct audits to ensure compliance within the programs, addressing any gaps proactively.

7. Data Analysis & Reporting : O Track and analyze HR metrics specific to each program, including turnover, engagement scores, and performance outcomes. O Prepare and present reports to program leaders, providing data-driven insights and recommendations for HR improvement. O Use data to identify trends and make informed decisions to optimize HR support for program-specific needs.

Dear #VLSI Folks,

Greetings from Juntran Technologies Pvt Ltd

• We are hiring #freshers #Mtech #VLSI specialization for the Bangalore location.

• Qualification : MTech/M.E in VLSI design/Embedded/Tele Communication/ECE.

• Pass out Year : <2021 to 2024.

• Interested Applicants can share their resumes to

Kindly refer and share for maximum reach.

Job Title- ASIC Frontend

Location- Bangalore, KA

Mode- Onsite

Job Type: Full-Time

Skill Required
: EIS: 3DEXPERIENCE Design and Engineering ~Blender~ EIS: ASIC Frontend - Modeling, RTL design and Implementation

Experience Range in Required Skills:6-8Yrs

Job Description
: Design 3D modeling, lighting, texturing and rendering as per communicated design Understanding the project requirements and conceptualizing new ideas Work with cross-functional teams create 3D assets according to requirements and drive successful launches of the Apps Able to set goals and achieve scheduled deadlines Translate the visual requirement into creative 3D design

Essential Skills
: 6 to 8years experience in 3DS Max or Maya or Blender

1. Good 3D design experience with 3DS Max or Maya or Blender

2. Fair knowledge in Supporting software as follows Substance 3D painter, Photoshop, V ray and Adobe CC.

3. 3D Modeling of Products

4. Photo-realistic material creation and rendering

5. Photo-realistic Lighting creation

6. Simple Animation

7. Knowledge in After effects and Arnold

8. Proven experience implementing best practices for 3D Design and re-use

9. Simple Character Design

10. Composition

ASIC Design Engineer

Location: Hyderabad

Experience: 5–10 years

Job Description

Key Responsibilities:

• Develop and implement RTL design for complex ASIC SoCs/IPs .
• Work on micro-architecture design, coding (Verilog/SystemVerilog ), and RTL integration .
• Perform design synthesis , lint , CDC/RDC checks, and timing closure.
• Collaborate with verification, physical design, and architecture teams to ensure first-pass silicon success.
• Debug design issues at block and SoC level, support verification and post-silicon validation.
• Contribute to low-power , high-performance design techniques for advanced technology nodes.

Required Skills:

• Strong expertise in RTL design using Verilog/SystemVerilog.
• Hands-on experience with ASIC flow: synthesis, STA , constraints , ECO .
• Knowledge of standard protocols (AXI, AHB, PCIe, DDR, Ethernet , etc.).
• Familiarity with power intent (UPF/CPF ) and clock /power domain crossings.
• Experience in working with EDA tools (Synopsys /Cadence /Mentor ).
• Good problem-solving and debugging skills.

About Company

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

ASIC/SOC Front End Design Engineer

Job description:

1. Setup ASIC QA flows for RTL design quality checks.

2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.

3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.

4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.

5. Checking the flow errors, design errors & violations and reviewing the reports.

6. Debugging CDC, RDC issues and come up with the RTL fixes.

7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.

8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.

9. Flows or Design porting to different technology libraries.

10. Generating RAMs based on targeted memory compilers and integrating with the RTL.

11. Running functional verification simulations as needed.

Job Requirements:

1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience

2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes

3. Modern SOC tools including Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, VCS simulation

4. Experience in signoff of front end quality checks & metrics for various milestones of the project

5. TCL, Perl, Python scripting

Experience: 3 to 5 years

Location: Hyderabad

Notice Period: Immediate

Role
- Senior ASIC/SoC RTL Engineer/Lead

Experience
- 7+ years

Location
- Hyderabad, Bangalore, Pune and Kochi

Notice Period
- Immediate to 60 days

JD of Senior ASIC/SoC RTL Engineer/Lead

• Expertise in SoC subsystem/IP design
• Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
• In depth knowledge on RTL quality checks (Lint, CDC)
• Knowledge of synthesis and low power is a plus
• Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
• Good understanding of timing concepts
• Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI
• Expertise in setting up and using tools like a. Spyglass Lint/CDC b. Synopsys DC c. Verdi/Xcellium
• Understanding of scripting languages like Make flow, Perl ,shell, python etc
• Understanding of processor architecture and/or ARM debug architecture is a plus
• Able to help and debug issues for multiple subsystems
• Able to create/review design documents for multiple subsystems
• Able to support physical design, verification, DFT and SW teams on design queries and reviews

ASIC Design Engineer

Location:
Hyderabad

Experience:
5–10 years

Job Description

Key Responsibilities:

• Develop and implement RTL design for complex
  ASIC SoCs/IPs
  .
• Work on
  micro-architecture
  design, coding (
  Verilog/SystemVerilog
  ), and RTL
  integration
  .
• Perform design
  synthesis
  ,
  lint
  ,
  CDC/RDC
  checks, and timing closure.
• Collaborate with verification, physical design, and architecture teams to ensure first-pass silicon success.
• Debug
  design issues at
  block
  and SoC level, support verification and post-silicon validation.
• Contribute to
  low-power
  ,
  high-performance
  design techniques for advanced technology nodes.

Required Skills:

• Strong expertise in RTL design using Verilog/SystemVerilog.
• Hands-on experience with ASIC flow: synthesis,
  STA
  ,
  constraints
  ,
  ECO
  .
• Knowledge of standard protocols (
  AXI, AHB, PCIe, DDR, Ethernet
  , etc.).
• Familiarity with power intent (
  UPF/CPF
  ) and
  clock
  /
  power
  domain crossings.
• Experience in working with
  EDA
  tools (
  Synopsys
  /
  Cadence
  /
  Mentor
  ).
• Good problem-solving and debugging skills.

About Company

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

This is what you are responsible for

Develop verification environments for modules, subsystems, top level and FPGA

Build models, checkers and random test frameworks using SystemVerilog and UVM

Participate in Low power analysis (UPF), power estimation, C modeling

Perform lint, CDC, code coverage, functional coverage

Formal verification of modules using SVA assertions

Necessary Qualifications

Experience in verifying complex subsystems and ASICs

Experience with building scalable verification environments from scratch

Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.

Exposure to FPGA emulation platforms, silicon bringup, and board debug

BTech/MTech in EE/CS with any level of experience