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Exp : 5 Years

Location : Bengaluru

Looking for an Analog Layout Engineer with GF Exp-Bengaluru based semiconductor organization.

Analog layout with at least 5 years' experience

• Experience with GF40nm node- Mandate

• Experience with PVS – LVS, DRC, Antenna & MRC

• Experience with delivering IP top-level for chip-level integration and doing all the necessary reviews & sign-offs

• Experience with coordinating the work of other layouts on sub-IP level would be a benefit

Job Title: BIW Layout Engineer

Location: Pune, India

Duration: 2 Months

Engagement Type: Contract / Freelance

Positions Available: 1

Job Overview

We are seeking a skilled and detail-oriented BIW (Body in White) Layout Engineer with 3–5 years of hands-on experience in AutoCAD. The ideal candidate will be responsible for developing and optimizing BIW layouts, ensuring alignment with engineering standards and production requirements.

Key Responsibilities

• Develop and modify BIW layouts using AutoCAD based on design specifications
• Collaborate with cross-functional teams including design, manufacturing, and quality
• Ensure compliance with safety, ergonomic, and manufacturing standards
• Analyze layout feasibility and suggest improvements for efficiency
• Support documentation and reporting of layout changes and updates

Required Qualifications

• Diploma or Bachelor's degree in Mechanical/Automobile Engineering or related field
• 3–5 years of experience in BIW layout design using AutoCAD
• Strong understanding of automotive manufacturing processes
• Ability to interpret engineering drawings and specifications

Job Types: Contractual / Temporary, Freelance

Contract length: 2 months

Pay: ₹11, ₹40,370.66 per month

Work Location: In person

Company Description

Thalia is a venture-funded technology business with facilities in Cwmbran, United Kingdom; Hyderabad, India; and Cologne, Germany. The company provides analog and mixed signal design solutions for integrated circuit (IC) manufacturers and IP companies utilizing unique design automation technology and strong value-added services capabilities. With support from investors like Mercia Fund Management and Finance Wales, along with grants from Innovate UK and The Welsh Government, Thalia enables customers to migrate designs, generate portfolios, and develop faster IPs, achieving reduced design cycles, lower costs, and shorter time to market. Thalia has successfully delivered numerous RF and baseband applications in collaboration with Tier 1 and Tier 2 vendors.

Role Description

This is a full-time on-site role for a Layout Design Engineer. The position is located in NCR region, India.
We are looking for a skilled and detail-oriented
Analog Layout Engineer

with hands-on experience in
CMOS

and
FinFET

process technologies up to 4nm process node. The ideal candidate will be responsible for full-custom layout design and physical verification of analog and mixed-signal IPs, ensuring high performance of analog circuits in state-of-the-art CMOS process technologies

Location: Noida/NCR, India

Experience: 2-4 Years

Qualification: B.E / B.Tech / M.Tech

Key Responsibilities:

• Perform
  full-custom layout

of analog and mixed-signal circuit blocks such as PLLs, ADCs, DACs, LDOs, Bandgap references, and other analog IP.
- Work closely with circuit designers to understand design intent and optimize for performance, area, and yield.
- Implement layout in advanced process nodes including
CMOS (e.g., 28nm, 16nm)

and
FinFET (e.g., 12nm, 8nm, 4nm)

technologies.
- Conduct
floorplanning

, device matching, shielding, routing, and parasitic-aware layout for high-performance analog blocks.
- Perform
DRC, LVS, ERC, and parasitic extraction (PEX)

using industry-standard tools.
- Participate in
design reviews

and collaborate with cross-functional teams to meet project milestones and quality requirements.
- Apply
layout best practices

to minimize mismatch, noise, and electromigration issues.
- Ensure design robustness against
process, voltage, and temperature (PVT)

variations.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 3+ years

of experience in analog/mixed-signal layout in advanced
CMOS and FinFET

nodes.
- Strong knowledge of layout tools such as
Cadence Virtuoso, Calibre, PVS

, or equivalent.
- In-depth understanding of
layout-dependent effects (LDE)

, matching techniques, and analog layout optimization.
- Familiarity with
EM/IR analysis

,
antenna effects

, and
ESD layout guidelines

.
- Experience working with
high-speed

and
low-power

analog design is a strong plus.
- Excellent communication and collaboration skills.

Preferred Skills:

• Experience with
  automated layout generation tools

(e.g., SKILL, Tcl scripting).
- Knowledge of
digital place & route flows

and
mixed-signal floorplanning

.
- Experience with
chip-level integration

and
top-level verification

.

We are looking for an Layout Design Engineer  – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

What you'll be doing:

• Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices.

• Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.

• IP layout will comprise of significant digital components and some analog components.

• Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts

• Follow company procedures and practices for IC layout activities.

What we need to see:

• 2+ years of experience in high performance analog layout in advanced CMOS process.

• BE/M-Tech in Electrical & Electronics or equivalent experience.

• Thorough knowledge of industry standard EDA tools for Cadence.

• Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.

• Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)

• Experience with floor planning, block level routing and macro level assembly.

• Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.

• Demonstrated experience with analog layout for silicon chips in mass production.

• Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.

• Experience working in distributed design team is a plus.

• Requires self-starter with the ability to define and adhere to a schedule.

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Position Name :- Layout Design Engineer

Experience :- 6 – 8 Years

Mandatory Skills

• Experience in schematic design, layout and technical documentation
• Experience in designing and verifying analog layouts, including power driver analog designs with multilayer layout.
• Experience in CAD tools (Altium),creation for library ,symbol, footprint and database addition
• Good in PCB fabrication principles/Process
• Sounds in interface drawing and ECU and PCB drawing creation
• Experience in PCB level testing

Tool Skills

• Altium, Auto-CAD

Additional Skills

• Troubleshooting issues with electronic circuits and identifying the root cause of the issue.
• Familiarity with electrical test equipment including oscilloscopes, signal generators, spectrum analyzers, network analyzers, and multimeters.

Job Description: PCB Layout Design Engineer

will be responsible for schematic entry in Cadstar and layout design for Control & Power electronics products. Good understanding on datasheets, symbols and foot print creation for complex customized parts and standard catalogue components.

Hands on experience in manual and high speed layout designs.

Skills/Abilities:

• Thorough experience in Cadstar design software’s for multilayer PCBs.

• PCB design from library creation to Gerber release for fabrication.

• Schematic symbol and foot print creation for complex components and library creation.

• Schematic entry, manual and high speed layout design.

• Constrains settings, mechanical considerations and stack up design.

• Knowledge in creepage/clearances and isolations, calculations for copper thickness.

• EMI/EMC considerations.

• DFx (DFm, DFa, DFt) considerations.

• Knowledge in DRC and Gerber generation process.

• Knowledge in Panel drawing design considerations.

• Interaction with Electrical, Mechanical, Thermal designers and NPI line.

• Interaction with PCB fabrication vendors for engineering queries.

Qualifications: BE/Btech degree in any of the following disciplines: Electrical /Electronics/ Communication

Experience: 2-6 years

Disclaimer:

"As part of your application, your personal data will be processed exclusively for recruitment-related purposes in compliance with applicable data protection laws and regulations."

Analog Layout Design Engineer with 3+ years of relevant work experience

You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients.

What you get:

• Inducted in the advanced Analog VLSI projects
• Get an opportunity to work with clients that are world-class VLSI MNCs

Skills:

• Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre)
• Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators
• Physical Verification ( LVS, DRC, ERC, ANT with Calibre)
• Ability to recognize and correct problematic circuit and layout structures
• Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected
• Ability to closely and independently work with Analog Designers to solve performance and area challenges

Traits:

• Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills
• Adaptable, Flexible, Global Approach/Synthesis, Creative
• Willing to work on customer site for deployment and support

• Good knowledge on different types of Memory architecture.

• Hands on experience on SRAM leafcell gds from scratch till top level integration.

• Expertise in working on memory layout design for advanced nodes

(TSMC : 7nm/5nm/3nm) is must.

• Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR.

• Proficient in Cadence virtuoso layout editor and caliber Physical verification flow.

• Synopsys Custom compiler experience is huge plus.

• Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm.

• Expertise working on FinFET architecture and challenges such as variability and manufacturability

• Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness

• Expertise in performing debugging of silicon failures and identify layout-related issues

• Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler

• Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules

• Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA)

• Provide feedback on circuit designs to improve layout efficiency

• Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits)

• Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL)

• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations

• Preferred resources with valid regional work permit.

Memory Layout Lead – Best-in-Class Semiconductor Memory IPs

As a Memory Layout Lead, you will drive the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs (SRAM, ROM, register files, CAMs, and more). You will own the complete layout strategy—from bitcell integration to periphery circuits—ensuring best-in-class PPA (performance, power, area) and yield, while meeting strict foundry rules.

Key Responsibilities

• Lead end-to-end layout design and floorplanning for advanced-node memory IPs.

• Deliver DRC/LVS/DFM-clean GDS with robust EM/IR reliability sign-off.

• Collaborate with circuit, CAD, and SoC integration teams for optimal implementation.

• Innovate layout techniques to achieve competitive density and performance targets.

• Provide comprehensive IP deliverables: GDSII, LEF, Liberty (.lib), Verilog models, and integration documentation.

Success Metrics

• Achieves world-class memory density and access times.

• Meets or exceeds power and yield requirements across PVT corners.

• Enables seamless integration into customer SoCs.