1,529 Typography jobs in India
Layout Design Engineer
Posted 1 day ago
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Job Description
We are looking for an Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs.
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.
What you'll be doing:
Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices.
Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.
IP layout will comprise of significant digital components and some analog components.
Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts
Follow company procedures and practices for IC layout activities.
What we need to see:
2+ years of experience in high performance analog layout in advanced CMOS process.
BE/M-Tech in Electrical & Electronics or equivalent experience.
Thorough knowledge of industry standard EDA tools for Cadence.
Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.
Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)
Experience with floor planning, block level routing and macro level assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.
Demonstrated experience with analog layout for silicon chips in mass production.
Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.
Experience working in distributed design team is a plus.
Requires self-starter with the ability to define and adhere to a schedule.
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
Pcb layout design engineer
Posted 1 day ago
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About SLTL Group,A renowned name, Sahajanand Laser Technology Ltd. Situated at Gandhinagar, Gujarat is a Pioneer in the manufacturing of laser marking & and engraving, laser cutting, laser welding, and solar cell scribing / micro-machining systems in the industrial segment. Fiber laser marking system with automation like Laser Marking for Bearing, Laser Marking for Piston rings, Laser Marking for Valves, Laser Marking for Nozzles, and Laser Marking for jewelry.Kindly go through our websites mentioned below for further details.Website: descriptionDesignation - Engineer/Sr EngineerDepartment - R and DExperience - 2 to 4 YearsLocation - Gandhinagar, Gujarat.Roles and responsibilities Design analog and digital circuits including signal conditioning, sensor interfaces, and control logic.Work on microcontroller/microprocessor-based hardware (e.g., STM32, NXP).Select components, design schematics, and create PCB layouts using Or CAD.Ensure signal integrity, thermal stability, and EMI robustness in circuit design.Develop DC-DC and DC-AC power converters, gate drivers, and protection circuits.Design and optimize motor drivers, or battery management circuits.Perform power and thermal calculations, simulate circuits (e.g., LTSpice, PLECS, PSIM)Conduct board-level and system-level testing using lab instruments (oscilloscopes, power analyzers, logic analyzers.Work closely with firmware, mechanical, and system teams for hardware integration.Maintain hardware documentation, BOMs, and version control.Required Skills & Competencies:B. E./B. Tech or M. E./M. Tech in Electronics & Communication Engineering.2–4 years of hands-on experience in both electronics circuit design and hardware debugging, testing.Strong understanding of embedded system hardware and power converter topologies.Proficiency in schematic capture, PCB layout, and circuit simulation tools.Strong analytical and problem-solving skills.Detail-oriented with a focus on quality and reliability.Ability to work in a collaborative, fast-paced development environment.Good documentation and communication skills.Experience with design for manufacturability (DFM) and design for test (DFT).
CAD Layout Design Engineer
Posted 1 day ago
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Job Description
We are now looking for a CAD Layout Design Engineer!
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today.
What you'll be doing:
You will be part of the groundbreaking "Layout Methodology" team with a charter to speed up layout creation, productivity and improve time to market of Nvidia digital IP like SRAM layouts and other custom layout blocks.
Be the first to conduct an in-depth study of new technology and enable the rest of the design teams to seamlessly start off on new/advanced layout technology.
Responsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.
Responsible for analysis of new technology and translating into guidelines for EMIR, DFM, SRAM layout guidelines etc.
Investigate next generation tools for layout creation.
Investigate the applications of Machine Learning / Deep Learning techniques for layout creation.
What we need to see:
BE/M-Tech in Electrical & Electronics or equivalent experience.
4+ years of experience.
Proven project cycle and tape out experience in SRAM memory layout design.
Experience in advanced technology nodes like 5 or 3 nanometers is a must.
Solid proficiency / expertise in the Cadence Skill language is a requirement for this job.
Experience with pCell development is a big plus.
Solid scripting skills in Python, Perl, Shell is a requirement.
Experience with Deep Learning or Machine Learning tools, Software will be a massive plus for this job and e xperience with EMIR tools is a big plus, ability to root cause and fix EMIR issues is a requirement.
Good social skills and be an excellent teammate.
Excellent presentation and influencing skills and ability to communicate new ideas/tools to other groups.
We are an equal opportunity employer and value diversity at our company. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
Packaging Design & Layout Design
Posted today
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Job Description
Date Opened
- 10/14/2024Job Type
- Full timeIndustry
- SemiconductorCity
- bengaluruState/Province
- karnataka bengaluruCountry
- IndiaZip/Postal Code
- **Job description**:
**Requirements**:
Strong Electrical engineering fundamentals and exposure on complete PCB Layout / Package Design cycle from Conceptualization to realization
- Proven experience in designing mock up modules in realizing the Package Design and working experience with EDA tools such as Cadence Allegro, OrCAD Schematic Capture etc., and industry popular packaging design tools.
- Very Good experience in managing a team of CAD engineers and guide them to ensure end goal with quality deliverables.
- Experience in designing complex Hi-Speed board layout designs involving HDI with buried Vias and Any layer to any layer interconnect technologies.
- Familiar with routing techniques that involves DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e, GB-Ethernet (10BASE-T / 100BASE-TX/1000BASE-T) etc.,
- Proficiency in advanced packaging design concepts (such as 2D, 2.5D, 3D and CoWos etc.,) with proven track record of delivering quality outputs.
- Good mentoring, Communication Skill and Team work
**Responsibilities**:
- Work with marketing and product development teams to understand the target audience, brand identity, and product requirements
- Present design solutions, concepts, and ideas to various stakeholders and incorporate feedback into the final design
- Keep up with consumer and market trends for packaging materials
- Responsible for designing and implementing reliable CAD designs for Layout & IC Packaging with hi-speed interface standards
- Architect the Package design as per the Client requirements and coordination to get it in physical form mentoring execution team
- Understand the impact of the packaging, such as the cost per unit of different packaging materials followed by creation of physical designs for packages and modules for chips such as memory, RF, cellular, and SoC
- Guiding the team leads / managers and identify Training Requirements for the team members to achieve the goal resulting in success of the organization
- The job involves co-ordination with Device packaging vendors, to ensure error free package design.
- Analyze existing packaging and come up with a new way to sell more products at a lower production price point
PCB Layout Design Engineer
Posted today
Job Viewed
Job Description
About SLTL Group,
A renowned name, Sahajanand Laser Technology Ltd. Situated at Gandhinagar, Gujarat is a Pioneer in the manufacturing of laser marking & and engraving, laser cutting, laser welding, and solar cell scribing / micro-machining systems in the industrial segment. Fiber laser marking system with automation like Laser Marking for Bearing, Laser Marking for Piston rings, Laser Marking for Valves, Laser Marking for Nozzles, and Laser Marking for jewelry.
Kindly go through our websites mentioned below for further details.
Website:
Job description
Designation - Engineer/Sr Engineer
Department - R and D
Experience - 2 to 4 Years
Location - Gandhinagar, Gujarat.
Roles and responsibilities
- Design analog and digital circuits including signal conditioning, sensor interfaces, and control logic.
- Work on microcontroller/microprocessor-based hardware (e.g., STM32, NXP).
- Select components, design schematics, and create PCB layouts using OrCAD.
- Ensure signal integrity, thermal stability, and EMI robustness in circuit design.
- Develop DC-DC and DC-AC power converters, gate drivers, and protection circuits.
- Design and optimize motor drivers, or battery management circuits.
- Perform power and thermal calculations, simulate circuits (e.g., LTSpice, PLECS, PSIM)
- Conduct board-level and system-level testing using lab instruments (oscilloscopes, power analyzers, logic analyzers.
- Work closely with firmware, mechanical, and system teams for hardware integration.
- Maintain hardware documentation, BOMs, and version control.
Required Skills & Competencies:
- B.E./B.Tech or M.E./M.Tech in Electronics & Communication Engineering.
- 2–4 years of hands-on experience in both electronics circuit design and hardware debugging, testing.
- Strong understanding of embedded system hardware and power converter topologies.
- Proficiency in schematic capture, PCB layout, and circuit simulation tools.
- Strong analytical and problem-solving skills.
- Detail-oriented with a focus on quality and reliability.
- Ability to work in a collaborative, fast-paced development environment.
- Good documentation and communication skills.
- Experience with design for manufacturability (DFM) and design for test (DFT).
eNVM Bitcell Layout Design Engineer
Posted 17 days ago
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Job Description
Tata Electronics is establishing one of India’s first advanced semiconductor fabs in Dholera, Gujarat, in partnership with Taiwan’s PSMC, marking a major step in India’s semiconductor manufacturing ecosystem.
Position: eNVM Bitcell Layout Design Engineer
We are looking for an engineer with strong hands-on experience in embedded Non-Volatile Memory (eNVM) Bitcell design . This is a specialized role (not a general VLSI/layout position).
What you will work on:
- Designing bitcells – the smallest circuit that stores one “0” or “1” inside a memory array.
- Focus on embedded memories such as Flash, MRAM, RRAM, or EEPROM.
- Collaborate with device and circuit engineers to ensure reliability, yield, and performance at advanced technology nodes.
What we are looking for:
Education: B.Tech/M.Tech/PhD in Electronics, VLSI, Microelectronics, or Semiconductor Engineering (Tier-1/Tier-2 preferred).
Experience:
- 5–12 years in semiconductor memory design.
- Proven experience in bitcell layout/design for eNVM/Flash/MRAM/EEPROM .
- Strong knowledge of transistor-level design, device physics, reliability, and DFM.
Senior Analog Layout Design Leads
Posted 25 days ago
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Job Description
Hi
Greetings from Eximietas Design!
We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team.
Locations: Bangalore.
Notice Period: 30 days or less preferred.
Job Description:
We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design.
Key Skills & Requirements:
- Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
- Solid understanding of how layout impacts circuit performance (speed, area, etc.).
- Ability to implement layouts that meet tight design constraints and deliver high quality.
- Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
- Familiarity with scripting languages (PERL/SKILL) is a plus.
- Strong communication skills and experience working with cross-functional teams.
If this opportunity interests you—or if you know someone suitable—please send your updated resume to:
Referrals are highly appreciated.
We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!
Maruthhi Naidu
Talent Associate - VLSI Manager
Eximietas Design - Visakhapatnam
.
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Senior Analog Layout Design Lead
Posted 25 days ago
Job Viewed
Job Description
Hi
Greetings from Eximietas Design!
We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 7–15 years of experience to join our growing team.
Locations: Hyderabad
Notice Period: 30 days or less preferred.
Job Description:
We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm) to contribute to cutting-edge analog layout design.
Key Skills & Requirements:
- Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
- Solid understanding of how layout impacts circuit performance (speed, area, etc.).
- Ability to implement layouts that meet tight design constraints and deliver high quality.
- Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
- Familiarity with scripting languages (PERL/SKILL) is a plus.
- Strong communication skills and experience working with cross-functional teams.
If this opportunity interests you—or if you know someone suitable—please send your updated resume to:
Referrals are highly appreciated.
We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!
Maruthhi Naidu
Talent Associate - VLSI Manager
Eximietas Design - Visakhapatnam
.