1,222 Typography jobs in India
Graphic Designer (Strong at PPT + Typography + Adobe Creative Suite + Graphic Design Principles)
Posted today
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Marketing Designer (Graphic Designer), Assurant-GCC, India
This position is responsible for creative and technical support of visual customer communications including the design, layout and preparation of marketing and business development collateral in print and digital media.
Position also includes learning new approaches, collateral channels and functional areas to broaden their support abilities for Assurant LOBs.
This position will be Bangalore/Chennai/Hyderabad at our India location.
What will be my duties and responsibilities in this job?
Strategic Development — 15%
Graphic Design and Motion Graphics — 85%
What are the requirements needed for this position?
What other the Preferred Experience, Skills, and Knowledge?
Graphic Designer (Strong at PPT + Typography + Adobe Creative Suite + Graphic Design Principles)
Posted today
Job Viewed
Job Description
Marketing Designer (Graphic Designer), Assurant-GCC, India
This position is responsible for creative and technical support of visual customer communications including the design, layout and preparation of marketing and business development collateral in print and digital media.
Position also includes learning new approaches, collateral channels and functional areas to broaden their support abilities for Assurant LOBs.
This position will be Bangalore/Chennai/Hyderabad at our India location.
What will be my duties and responsibilities in this job?
Strategic Development — 15%
Graphic Design and Motion Graphics — 85%
What are the requirements needed for this position?
What other the Preferred Experience, Skills, and Knowledge?
Layout Design Engineer
Posted today
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Job Description
We are looking for an Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs.
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.
What you'll be doing:
Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices.
Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs.
IP layout will comprise of significant digital components and some analog components.
Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts
Follow company procedures and practices for IC layout activities.
What we need to see:
2+ years of experience in high performance analog layout in advanced CMOS process.
BE/M-Tech in Electrical & Electronics or equivalent experience.
Thorough knowledge of industry standard EDA tools for Cadence.
Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required.
Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines)
Experience with floor planning, block level routing and macro level assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.
Demonstrated experience with analog layout for silicon chips in mass production.
Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred.
Experience working in distributed design team is a plus.
Requires self-starter with the ability to define and adhere to a schedule.
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
VLSI Layout Design Engineer
Posted 7 days ago
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Analog Layout Design Engineer with 3+ years of relevant work experience
You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients.
What you get:
- Inducted in the advanced Analog VLSI projects
- Get an opportunity to work with clients that are world-class VLSI MNCs
Skills:
- Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre)
- Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators
- Physical Verification ( LVS, DRC, ERC, ANT with Calibre)
- Ability to recognize and correct problematic circuit and layout structures
- Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected
- Ability to closely and independently work with Analog Designers to solve performance and area challenges
Traits:
- Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills
- Adaptable, Flexible, Global Approach/Synthesis, Creative
- Willing to work on customer site for deployment and support
AMS layout Design Engineer
Posted 7 days ago
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TSMC node 40nm with AMS layout experience.
Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation.
Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations.
Create floorplan
Performs DRC and takes corrective actions if needed until DRC is error free
Performs LVS and takes corrective actions if needed until result is successful
Performs layout in such a way that final result meets the foundry layout rules.
Provides extracted netlist for back annotation to DE as specified in the Design document, section layout.
Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout.
Adds extra useful information to the Block review document, section layout.
AMS layout Design Engineer
Posted 3 days ago
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Job Description
Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation.
Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations.
Create floorplan
Performs DRC and takes corrective actions if needed until DRC is error free
Performs LVS and takes corrective actions if needed until result is successful
Performs layout in such a way that final result meets the foundry layout rules.
Provides extracted netlist for back annotation to DE as specified in the Design document, section layout.
Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout.
Adds extra useful information to the Block review document, section layout.
VLSI Layout Design Engineer
Posted 4 days ago
Job Viewed
Job Description
You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients.
What you get:
Inducted in the advanced Analog VLSI projects
Get an opportunity to work with clients that are world-class VLSI MNCs
Skills:
Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre)
Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators
Physical Verification ( LVS, DRC, ERC, ANT with Calibre)
Ability to recognize and correct problematic circuit and layout structures
Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected
Ability to closely and independently work with Analog Designers to solve performance and area challenges
Traits:
Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills
Adaptable, Flexible, Global Approach/Synthesis, Creative
Willing to work on customer site for deployment and support
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CAD Layout Design Engineer
Posted today
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We are now looking for a CAD Layout Design Engineer!
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today.
What you'll be doing:
You will be part of the groundbreaking "Layout Methodology" team with a charter to speed up layout creation, productivity and improve time to market of Nvidia digital IP like SRAM layouts and other custom layout blocks.
Be the first to conduct an in-depth study of new technology and enable the rest of the design teams to seamlessly start off on new/advanced layout technology.
Responsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.
Responsible for analysis of new technology and translating into guidelines for EMIR, DFM, SRAM layout guidelines etc.
Investigate next generation tools for layout creation.
Investigate the applications of Machine Learning / Deep Learning techniques for layout creation.
What we need to see:
BE/M-Tech in Electrical & Electronics or equivalent experience.
4+ years of experience.
Proven project cycle and tape out experience in SRAM memory layout design.
Experience in advanced technology nodes like 5 or 3 nanometers is a must.
Solid proficiency / expertise in the Cadence Skill language is a requirement for this job.
Experience with pCell development is a big plus.
Solid scripting skills in Python, Perl, Shell is a requirement.
Experience with Deep Learning or Machine Learning tools, Software will be a massive plus for this job and e xperience with EMIR tools is a big plus, ability to root cause and fix EMIR issues is a requirement.
Good social skills and be an excellent teammate.
Excellent presentation and influencing skills and ability to communicate new ideas/tools to other groups.
We are an equal opportunity employer and value diversity at our company. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.