2982 Physical Design Engineer jobs in Bengaluru

Physical Design Engineer

Job Summary

The Physical Design Engineer will be responsible for the full-chip and/or block-level physical implementation of complex digital, mixed-signal, or RF integrated circuits from RTL to GDSII (the final manufacturing data). This role requires expertise in design methodologies to achieve optimal performance, power, and area (PPA) targets while ensuring manufacturability.

Key Responsibilities

• Physical Implementation Flow: Own and execute all phases of the physical design flow, including:
• Synthesis (RTL to Netlist).
• Floorplanning and Partitioning (defining block boundaries, pin placement, and power grid planning).
• Power Rail/Grid Design and analysis (EM/IR Drop).
• Place and Route (Placement of standard cells and macro blocks, followed by signal routing).
• Clock Tree Synthesis (CTS) : Design and optimize the clock network for minimal skew and latency.
• Timing Closure: Perform Static Timing Analysis (STA) , identify critical paths, and implement design optimization techniques (e.g., buffering, sizing, ECOs) to meet all frequency and timing constraints (setup/hold).

Required Qualifications and Skills

Education

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills & Experience

• Experience: 3+ years of experience in physical design, with a proven track record of tape-outs in advanced process nodes (e.g., 16nm, 7nm, 5nm, or lower).
• EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.

Soft Skills

• Excellent analytical, debugging, and problem-solving skills.
• Strong verbal and written communication skills.
• Ability to work effectively in a team environment and collaborate across different engineering disciplines.

Experience Level :- 3yrs to 15yrs

Notice Period :- Immediate to 60 Days

Work Location :- Bangalore

Mode of Work :- WFO

Employment Type :- Permanent

Greetings From TCS !

Role: Physical Design

Location: Bangalore

Experience Range: 5+ Years

Must-Have:

• Should have in depth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS
• Should have worked on the latest technology nodes (14nm or 2nm to 5nm)
• Must have experience in Static timing analysis
• Must have experience in Physical verification and appropriate fixes
• Should have worked on block level and top-level designs
• Strong problem-solving skills and communication skills
• Ability to mentor and work closely with junior engineers
• Tools: Synopsys and Cadence

Job Title: Physical Design Engineer

Experience: 4+ Years

Location: Banglaore/Hyderabad

Employment Type: Full-time

Industry: Semiconductors / VLSI / ASIC Design

Job Summary:

We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.

Key Responsibilities:

• Own block-level or full-chip implementation from RTL to GDSII.
• Perform:
• Floorplanning and placement
• Clock tree synthesis (CTS)
• Routing and optimization
• Run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks.
• Drive physical verification and signoff across various corners and scenarios.
• Collaborate with RTL, DFT, STA, and power teams for successful integration.
• Implement and debug low-power design techniques (UPF/CPF-based flows).
• Apply congestion analysis, ECOs, and timing fixes across critical paths.
• Optimize for performance, power, and area using EDA tools and foundry guidelines.
• Prepare design reports and support tapeout activities.

Required Skills and Experience:

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
• 4+years of experience in ASIC physical design.
• Strong hands-on experience with tools like:
• Place & Route: Cadence Innovus, Synopsys IC Compiler II (ICC2), Siemens Nitro
• STA: Synopsys PrimeTime
• Signoff: Calibre (DRC/LVS), RedHawk (IR/EM), Tempus
• Good understanding of physical design concepts: floorplan, placement, CTS, routing, ECO, and signoff.
• Familiarity with scripting languages: Tcl, Perl, Python for flow automation.
• Solid grasp of timing analysis, power grid design, and physical verification flows.

Interested can share Cv to

Physical Design Engineer - Senior / Lead

Job Description:

• Strong background in digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization.
• Tools Expertise : Proficient in Innovus , ICC2 , and Fusion Compiler for place and route, timing closure, and physical design sign-off.
• Physical Design : Experience in floorplanning, placement, routing, clock tree synthesis (CTS), and static timing analysis (STA).
• Optimization : Focus on power , performance , and area (PPA) optimization.
• Sign-off : Conduct DRC , LVS , and parasitic extraction for clean designs.
• Advanced Process Nodes : Experience with 7nm , 5nm , or lower process nodes.
• Cross-functional Collaboration : Work closely with design, verification, and manufacturing teams.
• Tape-out : Drive tape-out process and ensure high-quality designs.
• Qualifications : Bachelor’s or Master’s degree in Electrical Engineering, with 5+ years of experience.
• Preferred : Experience with DFM , DFT , and advanced packaging technologies.

Additional Skills :

• Proficiency in scripting languages like TCL , Perl , or Python for automating design tasks.
• Excellent problem-solving skills and attention to detail.
• Strong communication skills and the ability to collaborate effectively in a team environment.

Experience: 4 to 8 years

Location: Bangalore / Hyderabad

About Tata Electronics:

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.

Key Responsibilities:

• Hands-on experience with digital implementation flows (floorplanning, placement, CTS, routing, ECO, sign-off closure).
• Knowledge of analog layout constraints in PD flow.
• Perform top-level integration of analog and digital blocks in mixed-signal chips. Collaborate with analog layout engineers to ensure proper placement, matching, shielding, and parasitic control.
• Develop and execute floorplanning strategies that isolate sensitive analog regions from noisy digital domains.
• Run and debug DRC/LVS, parasitic extraction (PEX), and sign-off checks.
• Provide customer-facing support for enablement and design convergence.

• Required skills:
• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 8+ years of experience in physical design and implementation.
• Deep knowledge of RTL-to-GDSII flow with proven tape-out/sign-off experience.
• Hands-on expertise with EDA tools: Cadence Innovus, Synopsys DC/ICC2, Calibre, Redhawk/Voltus.

L&T Technologies (LTTS) is looking for Physical Design Engineers (PnR)with 4.5+ Years of experience.

Job Location : Bangalore

Please find the detailed job description below ::

• IP/Block level PnR activities from Netlist to GDS-II.

• Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV.

• Knowledge of industry stanrd E tools (Synops, Cadence, Mentor)

• Worked on DSM technologies, tsmc 5nm and below experience preferred.

• Knowledge of scripting skills.

• Minimum Experience : 4.5+ Years

Job Summary

We are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus , experience at N3 and below process nodes , and strong scripting and flow debugging skills .

Key Responsibilities

• Lead physical design activities from RTL to GDSII, ensuring high-quality and timely project delivery
• Execute floorplanning, placement, CTS, routing, and physical verification
• Develop and maintain automation scripts to streamline physical design tasks
• Collaborate with RTL, DFT, and verification teams to resolve design issues and achieve timing closure
• Optimize for power, performance, and area (PPA) to meet design targets
• Analyze timing, signal integrity, and power reports; implement necessary design changes
• Mentor junior engineers and promote continuous learning and improvement
• Stay current with physical design methodologies and integrate best practices

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in physical design with deep understanding of RTL to GDSII flow
• Proven hands-on experience with Cadence Innovus
• Demonstrated expertise in N3 and below technology nodes
• Strong scripting skills in Tcl, Perl, or Python , with ability to debug and enhance design flows
• Successful track record in timing closure, PPA optimization, and resolving complex design challenges
• Solid grasp of digital design principles including clock distribution, signal integrity, and power analysis
• Excellent problem-solving and communication skills

Preferred Skills

• Knowledge of low-power design techniques
• Familiarity with version control systems and collaborative development tools
• Experience with physical verification tools such as Calibre or Mentor Graphic

Full Chip Physical Design Engineer

Job Summary:

We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals.

Key Responsibilities:

• Drive full chip-level physical design flow from RTL to GDSII.
• Ownership of chip-level floorplanning, partitioning, and integration.
• Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues.
• Implement place & route flows including timing closure, IR/EM, and congestion optimization.
• Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations.
• Manage static timing analysis (STA) at top level and work closely with timing owners for signoff.
• Handle power planning and power domain implementation (UPF/CPF-based).
• Contribute to methodology improvements and automation.

Required Qualifications:

• Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field.
• 3–6 years of experience in physical design with at least one full chip tapeout.
• Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre).
• Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS.
• Proficiency in scripting languages like Tcl, Perl, Python, or Shell.
• Familiarity with hierarchical design and ECO flows.

Experience: 3 to 6 Years.

Location: Bangalore / Hyderabad .

Notice Period: Less than 30 days