16,861 Physical Design Engineer jobs in India

Physical Design Engineer

Job Summary

The Physical Design Engineer will be responsible for the full-chip and/or block-level physical implementation of complex digital, mixed-signal, or RF integrated circuits from RTL to GDSII (the final manufacturing data). This role requires expertise in design methodologies to achieve optimal performance, power, and area (PPA) targets while ensuring manufacturability.

Key Responsibilities

• Physical Implementation Flow: Own and execute all phases of the physical design flow, including:
• Synthesis (RTL to Netlist).
• Floorplanning and Partitioning (defining block boundaries, pin placement, and power grid planning).
• Power Rail/Grid Design and analysis (EM/IR Drop).
• Place and Route (Placement of standard cells and macro blocks, followed by signal routing).
• Clock Tree Synthesis (CTS) : Design and optimize the clock network for minimal skew and latency.
• Timing Closure: Perform Static Timing Analysis (STA) , identify critical paths, and implement design optimization techniques (e.g., buffering, sizing, ECOs) to meet all frequency and timing constraints (setup/hold).

Required Qualifications and Skills

Education

• Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills & Experience

• Experience: 3+ years of experience in physical design, with a proven track record of tape-outs in advanced process nodes (e.g., 16nm, 7nm, 5nm, or lower).
• EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.

Soft Skills

• Excellent analytical, debugging, and problem-solving skills.
• Strong verbal and written communication skills.
• Ability to work effectively in a team environment and collaborate across different engineering disciplines.

Experience Level :- 3yrs to 15yrs

Notice Period :- Immediate to 60 Days

Work Location :- Bangalore

Mode of Work :- WFO

Employment Type :- Permanent

eInfochips (An Arrow Company) Hiring Physical Design Engineer

Experience - 3+ Years

Location- Noida

<< Share resume at >>

Job description is as below:

* Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,

* Block level Physical Signoff,

* Block level Timing Signoff and ECO generation.

* Block level Power signoff.

* Good skill on Automation (Perl/Tcl/Awk/Python)

* Able to provide technical guidance to Junior Engineer and lead 4-6 engineers.

* Must have led small project team.

* Good in communication skill as he/she would be single point of contact for client.

* NO WORK FROM HOME.

Greetings From TCS !

Role: Physical Design

Location: Bangalore

Experience Range: 5+ Years

Must-Have:

• Should have in depth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS
• Should have worked on the latest technology nodes (14nm or 2nm to 5nm)
• Must have experience in Static timing analysis
• Must have experience in Physical verification and appropriate fixes
• Should have worked on block level and top-level designs
• Strong problem-solving skills and communication skills
• Ability to mentor and work closely with junior engineers
• Tools: Synopsys and Cadence

SKILLS AND EXPERIENCE REQUIREMENTS:

• Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience

• Excellent communication and problem-solving skills

• Excellent UNIX and scripting programming skills (Perl, Python and/or TCL)

• Strong understanding of digital circuits

• Experience with flow automation

• Expert knowledge of at least one EDA timing and constraints tool (Cadence Tempus, Synopsys PrimeTime)

• Experience with version control software (e.g. perforce, git)

• Highly motivated, self-starter with good interpersonal skills

Education Requirements

B. Tech / M. Tech (ECE)

Experience

3 to 13 Years

Job Location

Hyderabad

Shift

General (No WFH)

Work Week

Monday to Friday

He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.

· Provide technical guidance, mentoring to physical design engrs.

· Interface with front-end ASIC teams to resolve issues.

· Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.

· Timing closure on DDR2/DDR3/PCIE interfaces.

· Excellent communication skills.

· Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.

· Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.

· Expertise in scripting languages such as PERL, TCL.

· Strong Physical Verification skill set.

· Static Timing Analysis in Primetime or Primetime-SI.

· Good written and oral communication skills. Ability to clearly document plans.

· Ability to interface with different teams and prioritize work based on project needs.

Job Title: Physical Design Engineer

Experience: 4+ Years

Location: Banglaore/Hyderabad

Employment Type: Full-time

Industry: Semiconductors / VLSI / ASIC Design

Job Summary:

We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.

Key Responsibilities:

• Own block-level or full-chip implementation from RTL to GDSII.
• Perform:
• Floorplanning and placement
• Clock tree synthesis (CTS)
• Routing and optimization
• Run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks.
• Drive physical verification and signoff across various corners and scenarios.
• Collaborate with RTL, DFT, STA, and power teams for successful integration.
• Implement and debug low-power design techniques (UPF/CPF-based flows).
• Apply congestion analysis, ECOs, and timing fixes across critical paths.
• Optimize for performance, power, and area using EDA tools and foundry guidelines.
• Prepare design reports and support tapeout activities.

Required Skills and Experience:

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
• 4+years of experience in ASIC physical design.
• Strong hands-on experience with tools like:
• Place & Route: Cadence Innovus, Synopsys IC Compiler II (ICC2), Siemens Nitro
• STA: Synopsys PrimeTime
• Signoff: Calibre (DRC/LVS), RedHawk (IR/EM), Tempus
• Good understanding of physical design concepts: floorplan, placement, CTS, routing, ECO, and signoff.
• Familiarity with scripting languages: Tcl, Perl, Python for flow automation.
• Solid grasp of timing analysis, power grid design, and physical verification flows.

Interested can share Cv to

Physical Design Engineer - Senior / Lead

Job Description:

• Strong background in digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization.
• Tools Expertise : Proficient in Innovus , ICC2 , and Fusion Compiler for place and route, timing closure, and physical design sign-off.
• Physical Design : Experience in floorplanning, placement, routing, clock tree synthesis (CTS), and static timing analysis (STA).
• Optimization : Focus on power , performance , and area (PPA) optimization.
• Sign-off : Conduct DRC , LVS , and parasitic extraction for clean designs.
• Advanced Process Nodes : Experience with 7nm , 5nm , or lower process nodes.
• Cross-functional Collaboration : Work closely with design, verification, and manufacturing teams.
• Tape-out : Drive tape-out process and ensure high-quality designs.
• Qualifications : Bachelor’s or Master’s degree in Electrical Engineering, with 5+ years of experience.
• Preferred : Experience with DFM , DFT , and advanced packaging technologies.

Additional Skills :

• Proficiency in scripting languages like TCL , Perl , or Python for automating design tasks.
• Excellent problem-solving skills and attention to detail.
• Strong communication skills and the ability to collaborate effectively in a team environment.

Experience: 4 to 8 years

Location: Bangalore / Hyderabad