104 Team Leads jobs in Bengaluru

Overview

Hi

Greetings from Eximietas Design!

We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team.

Locations: Bangalore.

Notice Period: 30 days or less preferred.

Job Description:

We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design.

Key Skills & Requirements:

• Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
• Solid understanding of how layout impacts circuit performance (speed, area, etc.).
• Ability to implement layouts that meet tight design constraints and deliver high quality.
• Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
• Familiarity with scripting languages (PERL/SKILL) is a plus.
• Strong communication skills and experience working with cross-functional teams.

If this opportunity interests you—or if you know someone suitable—please send your updated resume to:

Referrals are highly appreciated.

We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!

Maruthhi Naidu

Talent Associate - VLSI Manager

Eximietas Design - Visakhapatnam

.

Hi

Greetings from Eximietas Design!

We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team.

Locations: Bangalore.

Notice Period: 30 days or less preferred.

Job Description:

We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design.

Key Skills & Requirements:

• Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
• Solid understanding of how layout impacts circuit performance (speed, area, etc.).
• Ability to implement layouts that meet tight design constraints and deliver high quality.
• Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
• Familiarity with scripting languages (PERL/SKILL) is a plus.
• Strong communication skills and experience working with cross-functional teams.

If this opportunity interests you—or if you know someone suitable—please send your updated resume to:

Referrals are highly appreciated.

We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!

Maruthhi Naidu

Talent Associate - VLSI Manager

Eximietas Design - Visakhapatnam

.

Role and Responsibilities

Skills and Experience

DFT Lead - 7 to 15 Years

Job Location : Bangalore| Hyderabad | Noida | Ahmedabad | Chennai

(NO WORK FROM HOME OR REMOTE WORK)

Job Specs:

• In depth knowledge of DFT concepts

• In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis

• In depth knowledge and hands on experience in MBIST insertion and Memory test validation

• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations

• Expertise in scripting languages such as perl, shell, etc.

• Experience in RTL and Gate level simulations of scan and MBIST test vectors

• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)

• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus

• Ability to work in an international team, dynamic environment

• Ability to learn and adapt to new tools and methodologies.

• Ability to do multi-tasking & work on several high priority designs in parallel.

• Excellent problem solving skills

• Excellent communication and team work skills and good English is required

DFT Lead - 7 to 15 Years

Job Location : Bangalore| Hyderabad | Noida | Ahmedabad | Chennai

(NO WORK FROM HOME OR REMOTE WORK)

Job Specs:

• In depth knowledge of DFT concepts

• In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis

• In depth knowledge and hands on experience in MBIST insertion and Memory test validation

• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations

• Expertise in scripting languages such as perl, shell, etc.

• Experience in RTL and Gate level simulations of scan and MBIST test vectors

• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)

• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus

• Ability to work in an international team, dynamic environment

• Ability to learn and adapt to new tools and methodologies.

• Ability to do multi-tasking & work on several high priority designs in parallel.

• Excellent problem solving skills

• Excellent communication and team work skills and good English is required

Hi

Greetings from Eximietas Design!

We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team.

Locations: Bangalore.

Notice Period: 30 days or less preferred.

Job Description:

We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design.

Key Skills & Requirements:

• Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
• Solid understanding of how layout impacts circuit performance (speed, area, etc.).
• Ability to implement layouts that meet tight design constraints and deliver high quality.
• Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
• Familiarity with scripting languages (PERL/SKILL) is a plus.
• Strong communication skills and experience working with cross-functional teams.

If this opportunity interests you—or if you know someone suitable—please send your updated resume to:

Referrals are highly appreciated.

We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!

Maruthhi Naidu

Talent Associate - VLSI Manager

Eximietas Design - Visakhapatnam

.

Hi

Greetings from Eximietas Design!

We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team.

Locations: Bangalore.

Notice Period: 30 days or less preferred.

Job Description:

We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design.

Key Skills & Requirements:

• Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
• Solid understanding of how layout impacts circuit performance (speed, area, etc.).
• Ability to implement layouts that meet tight design constraints and deliver high quality.
• Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
• Familiarity with scripting languages (PERL/SKILL) is a plus.
• Strong communication skills and experience working with cross-functional teams.

If this opportunity interests you—or if you know someone suitable—please send your updated resume to:

Referrals are highly appreciated.

We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design!

Maruthhi Naidu

Talent Associate - VLSI Manager

Eximietas Design - Visakhapatnam

.